; TASKING TriCore C compiler v1.5r1 Build 322 SN 00090364
; options: -e -A1 -g -O0 -Id:\ctri\include -s -N8 -zTC112_COR1 -zTC112_COR4
;          -zTC112_COR10 -zTC112_COR13 -zTC112_COR14 -zTC112_COR16 -zTC112_COR17
	.name	"main"
	.symb	TOOL, "TASKING TriCore C compiler v1.5", 1
	.symb	TYPE, 256, "bit", 'g', 0, 1
	.symb	FILE, "main.c"
; file "main.c":
;    1 |//****************************************************************************
;    2 |// @Module        Project Settings
;    3 |// @Filename      MAIN.C
;    4 |// @Project       Test_TC1775B.dav
;    5 |//----------------------------------------------------------------------------
;    6 |// @Controller    Infineon TC1775 B-Step
;    7 |//
;    8 |// @Compiler      Tasking
;    9 |//
;   10 |// @Codegenerator 2.2
;   11 |//
;   12 |// @Description   This file contains the project initialization function.
;   13 |//
;   14 |//----------------------------------------------------------------------------
;   15 |// @Date          12.06.2002 17:31:40
;   16 |//
;   17 |//****************************************************************************
;   18 |
;   19 |// USER CODE BEGIN (MAIN_General,1)
;   20 |
;   21 |// USER CODE END
;   22 |
;   23 |
;   24 |
;   25 |//****************************************************************************
;   26 |// @Project Includes
;   27 |//****************************************************************************
;   28 |
;   29 |#include "MAIN.H"
	.symb	FILE, "MAIN.H"
	.symb	TYPE, 257, "uword", 'T', #18
	.symb	FILE, "TC1775BRegs.h"
	.symb	ENDF
	.symb	FILE, "IO.H"
	.symb	ENDF
	.symb	FILE, "ASC0.H"
	.symb	TYPE, 258, "ushort", 'T', #5
	.symb	ENDF
	.symb	FILE, "ASC1.H"
	.symb	ENDF
	.symb	FILE, "CAN.H"
	.symb	TYPE, 259, "ubyte", 'T', #3
	.symb	TYPE, 260, 'Z', #3, 7
	.symb	TYPE, 262, 'S', 20,\
		 "usMsgCfg", #5, 0,\
		 "uwID", #18, 2,\
		 "uwMask", #18, 6,\
		 "ubData", #260, 10,\
		 "usCounter", #5, 18
	.symb	TYPE, 263, "TCAN_SWObj", 'T', #262
	.symb	ENDF
	.symb	ENDF
;   30 |
;   31 |// USER CODE BEGIN (MAIN_General,2)
;   32 |#include "stdio.h"
	.symb	FILE, "d:\\ctri\\include\\stdio.h"
	.symb	FILE, "d:\\ctri\\include\\stdarg.h"
	.symb	ENDF
	.symb	TYPE, 265, 'P', #2
	.symb	TYPE, 266, "_iobuf", 'S', 24,\
		 "_ptr", #265, 0,\
		 "_base", #265, 4,\
		 "_cnt", #16, 8,\
		 "_bufsiz", #16, 12,\
		 "_flag", #5, 16,\
		 "_file", #2, 18,\
		 "_wcnt", #16, 20
	.symb	TYPE, 267, "FILE", 'T', #266
	.symb	TYPE, 268, "va_list", 'T', #265
	.symb	TYPE, 269, "size_t", 'T', #18
	.symb	TYPE, 270, "fpos_t", 'T', #7
	.symb	TYPE, 271, "off_t", 'T', #6
	.symb	ENDF
;   33 |// USER CODE END
;   34 |
;   35 |
;   36 |//****************************************************************************
;   37 |// @Macros
;   38 |//****************************************************************************
;   39 |
;   40 |// USER CODE BEGIN (MAIN_General,3)
;   41 |
;   42 |// USER CODE END
;   43 |
;   44 |
;   45 |//****************************************************************************
;   46 |// @Defines
;   47 |//****************************************************************************
;   48 |
;   49 |#define RESET_INDICATOR     ((RST_SR & 0xFF000000) >> 24)
;   50 |#define DEEPSLEEP_WAKEUP    0x80
;   51 |#define WATCHDOG_RESET      0x40
;   52 |#define SOFTWARE_RESET      0x20
;   53 |#define HARDWARE_RESET      0x10
;   54 |#define POWERON_RESET       0x08
;   55 |
;   56 |// USER CODE BEGIN (MAIN_General,4)
;   57 |
;   58 |// USER CODE END
;   59 |
;   60 |
;   61 |//****************************************************************************
;   62 |// @Typedefs
;   63 |//****************************************************************************
;   64 |
;   65 |// USER CODE BEGIN (MAIN_General,5)
;   66 |
;   67 |// USER CODE END
;   68 |
;   69 |
;   70 |//****************************************************************************
;   71 |// @Imported Global Variables
;   72 |//****************************************************************************
;   73 |
;   74 |// USER CODE BEGIN (MAIN_General,6)
;   75 |
;   76 |// USER CODE END
;   77 |
;   78 |
;   79 |//****************************************************************************
;   80 |// @Global Variables
;   81 |//****************************************************************************
;   82 |
;   83 |// USER CODE BEGIN (MAIN_General,7)
;   84 |unsigned char ucErrorFlag;
;   85 |unsigned int uiPRG_Offset;
;   86 |// USER CODE END
;   87 |
;   88 |
;   89 |//****************************************************************************
;   90 |// @External Prototypes
;   91 |//****************************************************************************
;   92 |
;   93 |// USER CODE BEGIN (MAIN_General,8)
;   94 |extern void test (void);
;   95 |// USER CODE END
;   96 |
;   97 |
;   98 |//****************************************************************************
;   99 |// @Prototypes Of Local Functions
;  100 |//****************************************************************************
;  101 |
;  102 |// USER CODE BEGIN (MAIN_General,9)
;  103 |
;  104 |// USER CODE END
;  105 |
;  106 |
;  107 |//****************************************************************************
;  108 |// @Function      void MAIN_vInit(void) 
;  109 |//
;  110 |//----------------------------------------------------------------------------
;  111 |// @Description   This function initializes the microcontroller.
;  112 |//
;  113 |//----------------------------------------------------------------------------
;  114 |// @Returnvalue   None
;  115 |//
;  116 |//----------------------------------------------------------------------------
;  117 |// @Parameters    None
;  118 |//
;  119 |//----------------------------------------------------------------------------
;  120 |// @Date          12.06.2002
;  121 |//
;  122 |//****************************************************************************
;  123 |
;  124 |// USER CODE BEGIN (Init,1)
;  125 |
;  126 |// USER CODE END
;  127 |
;  128 |void MAIN_vInit(void)
;  129 |{
	.sdecl	"code.main",CODE
	.sect	"code.main"
	.align	4
	.symb	LINE, 129
	.symb	TYPE, 272, 'X', 8, #1, 26, 0
	.symb	GFUN, "MAIN_vInit", MAIN_vInit, #272, 0, 0, 0
	.symb	ALAB, MAIN_vInit, #272
MAIN_vInit:
	.symb	SOFF, 0
;  130 |  // USER CODE BEGIN (Init,2)
;  131 |
;  132 |  // USER CODE END
;  133 |
;  134 |  //// -----------------------------------------------------------------------
;  135 |  //// Begin of Important Settings for the Start-Up File
;  136 |  //// -----------------------------------------------------------------------
;  137 |  ///  All following settings must be set in the start-up file. You can use 
;  138 |  ///  DAvE's project file (*.dpt) to include this register values into your 
;  139 |  ///  compiler EDE.
;  140 |
;  141 |    ///  ---------------------------------------------------------------------
;  142 |    ///  Bus Control Unit (BCU):
;  143 |    ///  ---------------------------------------------------------------------
;  144 |    ///  BCU starvation protection is enabled
;  145 |    ///  BCU power saving is disabled
;  146 |    ///  the debug trace is enabled. Error information is captured in 
;  147 |    ///  register BCEADD, BCEDAT and BCECON
;  148 |    ///  sample period of request for starvation protection: 64
;  149 |    ///  BCU bus time-out value: 65536 cycles
;  150 |
;  151 |    //// this register must be set in the start-up file
;  152 |    //// BCU_CON  =  0x4009FFFF;
;  153 |
;  154 |    ///  ---------------------------------------------------------------------
;  155 |    ///  Program Memory Unit (PMU):
;  156 |    ///  ---------------------------------------------------------------------
;  157 |    ///  ICACHE settings:
;  158 |    ///  the instruction cache is enabled
;  159 |    ///  the instruction cache is bypassed
;  160 |
;  161 |    //// this register must be set in the start-up file
;  162 |    //// PMU_CON  =  0x04003F06;
;  163 |
;  164 |    ///  external flash settings:
;  165 |    ///  min. wait cycles between consecutive burst accesses from external 
;  166 |    ///  Flash: 7 wait cycles
;  167 |    ///  read wait cycles between the initial address and the first data 
;  168 |    ///  cycle: 7 wait cycles
;  169 |    ///  two address cycles
;  170 |    ///  two data cycles
;  171 |    ///  unlimeted numbers of linear Flash burst data cycles
;  172 |    ///  max. number of burst data cycle: 1 data accesses
;  173 |    ///  #WAIT input operates as a wait data bus function on bursts
;  174 |    ///  #CS0 is activated during burst mode
;  175 |
;  176 |    //// this register must be set in the start-up file
;  177 |    //// PMU_EIFCON  =  0x0000005F;
;  178 |
;  179 |    ///  ---------------------------------------------------------------------
;  180 |    ///  External Bus Unit (EBU):
;  181 |    ///  ---------------------------------------------------------------------
;  182 |
;  183 |    ///  enable the EBU module
;  184 |
;  185 |    //// this register must be set in the start-up file
;  186 |    //// EBU_CLC  =  0x00000000;
;  187 |
;  188 |    ///  External Arbitration:
;  189 |    ///  EBU is external master
;  190 |    ///  arbitration inputs are asynchronous
;  191 |    ///  external bus will not be locked after EBU gained ownership
;  192 |    ///  disable external accesses to FPI bus
;  193 |    ///  disable external address extension register reconfiguration
;  194 |    ///  all accesses from external master are performed in user mode
;  195 |    ///  disable Time-out
;  196 |    ///  chip select triggered driver turn-around inactive cycles: 0
;  197 |    ///  read-write triggered driver turn-around inactive cycles: 0
;  198 |
;  199 |    //// this register must be set in the start-up file
;  200 |    //// EBU_CON  =  0x00000060;
;  201 |
;  202 |    ///  Overlay Memory:
;  203 |    ///  do not activate chip select #CSOVL on an access to memory region 0
;  204 |    ///  do not activate chip select #CSOVL on an access to memory region 1
;  205 |    ///  do not activate chip select #CSOVL on an access to memory region 2
;  206 |    ///  do not activate chip select #CSOVL on an access to memory region 3
;  207 |
;  208 |    //// this register must be set in the start-up file
;  209 |    //// EBU_EMUCON  =  0x00000000;
;  210 |
;  211 |    ///  Address Region 0:
;  212 |    ///  enable memory region 0
;  213 |    ///  length of the region: 4 Mbyte
;  214 |    ///  relevant start address (A31 : A0): 0xB0000000
;  215 |    ///  writes to memory region are enabled
;  216 |    ///  address generation: demuxed address mode
;  217 |    ///  external device data width: 32-bit
;  218 |    ///  address latch enable (ALE) duration: 3 cycles
;  219 |    ///  byte control signal timing mode: chipselect mode
;  220 |    ///  cycle 0 is not generated
;  221 |    ///  variable waitstate insertion is disabled
;  222 |    ///  pin #WAIT is low active
;  223 |    ///  read cycle multiplier is 1
;  224 |    ///  read access waitstates: 48
;  225 |    ///  cycle multiplier is 16
;  226 |    ///  write access waitstates: 112
;  227 |    ///  hold/pause cycle waitstates: 48
;  228 |    ///  recovery cycles waitstates: 48
;  229 |
;  230 |    //// this register must be set in the start-up file
;  231 |    //// EBU_ADDSEL0  =  0xB0000051;
;  232 |    //// EBU_BUSCON0  =  0x600261FF;
;  233 |
;  234 |    ///  Address Region 1:
;  235 |    ///  enable memory region 1
;  236 |    ///  length of the region: 1 Mbyte
;  237 |    ///  relevant start address (A31 : A0): 0xA0000000
;  238 |    ///  writes to memory region are enabled
;  239 |    ///  address generation: demuxed address mode
;  240 |    ///  external device data width: 32-bit
;  241 |    ///  address latch enable (ALE) duration: 3 cycles
;  242 |    ///  byte control signal timing mode: chipselect mode
;  243 |    ///  cycle 0 is not generated
;  244 |    ///  variable waitstate insertion is disabled
;  245 |    ///  pin #WAIT is low active
;  246 |    ///  read cycle multiplier is 1
;  247 |    ///  read access waitstates: 48
;  248 |    ///  cycle multiplier is 16
;  249 |    ///  write access waitstates: 112
;  250 |    ///  hold/pause cycle waitstates: 48
;  251 |    ///  recovery cycles waitstates: 48
;  252 |
;  253 |    //// this register must be set in the start-up file
;  254 |    //// EBU_ADDSEL1  =  0xA0000071;
;  255 |    //// EBU_BUSCON1  =  0x600261FF;
;  256 |
;  257 |    ///  Address Region 2:
;  258 |    ///  enable memory region 2
;  259 |    ///  length of the region: 1 Mbyte
;  260 |    ///  relevant start address (A31 : A0): 0xA0100000
;  261 |    ///  writes to memory region are enabled
;  262 |    ///  address generation: demuxed address mode
;  263 |    ///  external device data width: 32-bit
;  264 |    ///  address latch enable (ALE) duration: 3 cycles
;  265 |    ///  byte control signal timing mode: chipselect mode
;  266 |    ///  cycle 0 is not generated
;  267 |    ///  variable waitstate insertion is disabled
;  268 |    ///  pin #WAIT is low active
;  269 |    ///  read cycle multiplier is 1
;  270 |    ///  read access waitstates: 48
;  271 |    ///  cycle multiplier is 16
;  272 |    ///  write access waitstates: 112
;  273 |    ///  hold/pause cycle waitstates: 48
;  274 |    ///  recovery cycles waitstates: 48
;  275 |
;  276 |    //// this register must be set in the start-up file
;  277 |    //// EBU_ADDSEL2  =  0xA0100071;
;  278 |    //// EBU_BUSCON2  =  0x600261FF;
;  279 |
;  280 |    ///  Address Region 3:
;  281 |    ///  enable memory region 3
;  282 |    ///  length of the region: 8 Mbyte
;  283 |    ///  relevant start address (A31 : A0): 0xB0800000
;  284 |    ///  writes to memory region are enabled
;  285 |    ///  address generation: demuxed address mode
;  286 |    ///  external device data width: 16-bit
;  287 |    ///  address latch enable (ALE) duration: 3 cycles
;  288 |    ///  byte control signal timing mode: chipselect mode
;  289 |    ///  cycle 0 is not generated
;  290 |    ///  variable waitstate insertion is disabled
;  291 |    ///  pin #WAIT is low active
;  292 |    ///  read cycle multiplier is 16
;  293 |    ///  read access waitstates: 2032
;  294 |    ///  cycle multiplier is 16
;  295 |    ///  write access waitstates: 112
;  296 |    ///  hold/pause cycle waitstates: 48
;  297 |    ///  recovery cycles waitstates: 48
;  298 |
;  299 |    //// this register must be set in the start-up file
;  300 |    //// EBU_ADDSEL3  =  0xB0800041;
;  301 |    //// EBU_BUSCON3  =  0x60C1FFFF;
;  302 |
;  303 |    ///  Emulator Address Region :
;  304 |    ///  enable emulator memory region
;  305 |    ///  length of the region: 16 Mbyte
;  306 |    ///  relevant start address (A31 : A0): 0xBE000000
;  307 |    ///  writes to memory region are enabled
;  308 |    ///  address generation: demuxed address mode
;  309 |    ///  external device data width: 32-bit
;  310 |    ///  address latch enable (ALE) duration: 0 cycles
;  311 |    ///  byte control signal timing mode: chipselect mode
;  312 |    ///  cycle 0 is generated
;  313 |    ///  asynchronous waitstate insertion
;  314 |    ///  pin #WAIT is low active
;  315 |    ///  read cycle multiplier is 1
;  316 |    ///  read access waitstates: 1
;  317 |    ///  cycle multiplier is 1
;  318 |    ///  write access waitstates: 2
;  319 |    ///  hold/pause cycle waitstates: 0
;  320 |    ///  recovery cycles waitstates: 0
;  321 |
;  322 |    //// this register must be set in the start-up file
;  323 |    //// EBU_EMUAS  =  0xBE000031;
;  324 |    //// EBU_EMUBC  =  0x00160280;
;  325 |
;  326 |  //// -----------------------------------------------------------------------
;  327 |  //// End of Important Settings for the Start-Up File
;  328 |  //// -----------------------------------------------------------------------
;  329 |
;  330 |  ///  -----------------------------------------------------------------------
;  331 |  ///  Clock System:
;  332 |  ///  -----------------------------------------------------------------------
;  333 |  ///  - external clock frequency: 16,000 MHz
;  334 |  ///  - PLL operation (pin BYPASS = 0)
;  335 |  ///  - clock factor (N-factor): 10 (pins CLKSEL[2:0] = 0x2)
;  336 |  ///  - VCO output frequency: 160,000 MHz
;  337 |  ///  - clock divider (K-factor): 4
;  338 |  ///  - system clock: 40,000 MHz
;  339 |
;  340 |  MAIN_vResetENDINIT();
	.symb	LINE, 340
	ld.w	d4,-268435424
	mov16	d15,#-2				; -2
	and16	d4,d15
	callg	MAIN_vWriteWDTCON0
;  341 |  PLL_CLC        =  0x00020000;  // load PLL clock control register
	.symb	LINE, 341
	movh	d15,#0x2
	st.w	-268435392,d15
;  342 |  MAIN_vSetENDINIT();
	.symb	LINE, 342
	ld.w	d4,-268435424
	or	d4,d4,#1
	callg	MAIN_vWriteWDTCON0
;  343 |
;  344 |  ///  -----------------------------------------------------------------------
;  345 |  ///  Interrupt System:
;  346 |  ///  -----------------------------------------------------------------------
;  347 |  ///  - four arbitration cycles (max. 255 interrupt sources)
;  348 |  ///  - two clocks per arbitration cycle
;  349 |
;  350 |  MTCR(0xFE2C,  0x00000000);     // load CPU interrupt control register
	.symb	LINE, 350
	mov16	d15,#0				; 0
	mtcr	#65068,d15			; 65068
;  351 |  ISYNC();
	.symb	LINE, 351
	isync
;  352 |
;  353 |  ///  -----------------------------------------------------------------------
;  354 |  ///  Peripheral Control Processor (PCP):
;  355 |  ///  -----------------------------------------------------------------------
;  356 |  ///  - four arbitration cycles (max. 255 PCP channels)
;  357 |  ///  - two clocks per arbitration cycle
;  358 |  ///  - use Full Context save area (R[0] - R[7])
;  359 |  ///  - channel start at context PC
;  360 |  ///  - the PCP error interrupt is disabled
;  361 |  ///  - PRAM partitioning is disabled
;  362 |  ///  - channel watchdog is disabled
;  363 |
;  364 |  MAIN_vResetENDINIT();
	.symb	LINE, 364
	ld.w	d4,-268435424
	mov16	d15,#-2				; -2
	and16	d4,d15
	callg	MAIN_vWriteWDTCON0
;  365 |  PCP_CS         =  0x00020800;  // load PCP control and status register
	.symb	LINE, 365
	mov.u	d15,#0x800
	addih	d15,d15,#0x2
	st.w	-268419312,d15
;  366 |  MAIN_vSetENDINIT();
	.symb	LINE, 366
	ld.w	d4,-268435424
	or	d4,d4,#1
	callg	MAIN_vWriteWDTCON0
;  367 |
;  368 |  PCP_ICR        =  0x00000000;  // load PCP interrupt control register
	.symb	LINE, 368
	mov16	d15,#0
	st.w	-268419296,d15
;  369 |
;  370 |  //   -----------------------------------------------------------------------
;  371 |  //   Initialization of the Peripherals:
;  372 |  //   -----------------------------------------------------------------------
;  373 |  //   initializes the Parallel Ports
;  374 |  IO_vInit();
	.symb	LINE, 374
	callg	IO_vInit
;  375 |
;  376 |  //   initializes the Asynchronous Synchronous Serial Interface 0 (ASC0)
;  377 |  ASC0_vInit();
	.symb	LINE, 377
	callg	ASC0_vInit
;  378 |
;  379 |  //   initializes the Asynchronous Synchronous Serial Interface 1 (ASC1)
;  380 |  ASC1_vInit();
	.symb	LINE, 380
	callg	ASC1_vInit
;  381 |
;  382 |  //   initializes the TwinCAN Controller 
;  383 |  CAN_vInit();
	.symb	LINE, 383
	callg	CAN_vInit
;  384 |
;  385 |
;  386 |  // USER CODE BEGIN (Init,3)
;  387 |
;  388 |  // USER CODE END
;  389 |
;  390 |  ///  -----------------------------------------------------------------------
;  391 |  ///  System Start Conditions:
;  392 |  ///  -----------------------------------------------------------------------
;  393 |
;  394 |  //// - the CPU interrupt system is globally disabled
;  395 |  DISABLE();
	.symb	LINE, 395
	disable
;  396 |
;  397 |  //// - the PCP interrupt system is globally disabled
;  398 |
;  399 |
;  400 |  // USER CODE BEGIN (Init,4)
;  401 |
;  402 |  // USER CODE END
;  403 |
;  404 |} //  End of function MAIN_vInit
	.symb	LINE, 404
	ret16
	.symb	EFUN
;  405 |
;  406 |
;  407 |//****************************************************************************
;  408 |// @Function      void MAIN_vWriteWDTCON0(uword uwValue) 
;  409 |//
;  410 |//----------------------------------------------------------------------------
;  411 |// @Description   This function writes the parameter uwValue to the WDT_CON0 
;  412 |//                register which is password protected. 
;  413 |//
;  414 |//----------------------------------------------------------------------------
;  415 |// @Returnvalue   None
;  416 |//
;  417 |//----------------------------------------------------------------------------
;  418 |// @Parameters    uwValue: 
;  419 |//                Value for the WDTCON0 register
;  420 |//
;  421 |//----------------------------------------------------------------------------
;  422 |// @Date          12.06.2002
;  423 |//
;  424 |//****************************************************************************
;  425 |
;  426 |// USER CODE BEGIN (WriteWDTCON0,1)
;  427 |
;  428 |// USER CODE END
;  429 |
;  430 |void MAIN_vWriteWDTCON0(uword uwValue)
;  431 |{
	.symb	LINE, 431
	.symb	TYPE, 273, 'g', 0, 1
	.symb	TYPE, 274, 'g', 0, 1
	.symb	TYPE, 275, 'g', 0, 1
	.symb	TYPE, 276, 'g', 0, 1
	.symb	TYPE, 277, 'g', 0, 1
	.symb	TYPE, 278, 'g', 0, 1
	.symb	TYPE, 279, 'g', 0, 1
	.symb	TYPE, 280, 'g', 0, 1
	.symb	TYPE, 281, 'g', 0, 1
	.symb	TYPE, 282, 'g', 0, 1
	.symb	TYPE, 283, 'g', 0, 1
	.symb	TYPE, 284, 'g', 0, 1
	.symb	TYPE, 285, 'g', 0, 1
	.symb	TYPE, 286, 'g', 0, 1
	.symb	TYPE, 287, 'g', 0, 1
	.symb	TYPE, 288, 'g', 0, 1
	.symb	TYPE, 289, 'g', 0, 1
	.symb	TYPE, 290, 'g', 0, 1
	.symb	TYPE, 291, 'g', 0, 1
	.symb	TYPE, 292, 'g', 0, 1
	.symb	TYPE, 293, 'g', 0, 1
	.symb	TYPE, 294, 'g', 0, 1
	.symb	TYPE, 295, 'g', 0, 1
	.symb	TYPE, 296, 'g', 0, 1
	.symb	TYPE, 297, 'g', 0, 1
	.symb	TYPE, 298, 'g', 0, 1
	.symb	TYPE, 299, 'g', 0, 1
	.symb	TYPE, 300, 'g', 0, 1
	.symb	TYPE, 301, 'g', 0, 1
	.symb	TYPE, 302, 'g', 0, 1
	.symb	TYPE, 303, 'g', 0, 1
	.symb	TYPE, 304, 'g', 0, 1
	.symb	TYPE, 305, 'S', 4,\
		 "bit0", #273, 0,\
		 "bit1", #274, 1,\
		 "bit2", #275, 2,\
		 "bit3", #276, 3,\
		 "bit4", #277, 4,\
		 "bit5", #278, 5,\
		 "bit6", #279, 6,\
		 "bit7", #280, 7,\
		 "bit8", #281, 8,\
		 "bit9", #282, 9,\
		 "bit10", #283, 10,\
		 "bit11", #284, 11,\
		 "bit12", #285, 12,\
		 "bit13", #286, 13,\
		 "bit14", #287, 14,\
		 "bit15", #288, 15,\
		 "bit16", #289, 16,\
		 "bit17", #290, 17,\
		 "bit18", #291, 18,\
		 "bit19", #292, 19,\
		 "bit20", #293, 20,\
		 "bit21", #294, 21,\
		 "bit22", #295, 22,\
		 "bit23", #296, 23,\
		 "bit24", #297, 24,\
		 "bit25", #298, 25,\
		 "bit26", #299, 26,\
		 "bit27", #300, 27,\
		 "bit28", #301, 28,\
		 "bit29", #302, 29,\
		 "bit30", #303, 30,\
		 "bit31", #304, 31
	.symb	TYPE, 306, "T_Reg32", 'T', #305
	.symb	TYPE, 307, 'X', 8, #1, 26, 1, #18
	.symb	GFUN, "MAIN_vWriteWDTCON0", MAIN_vWriteWDTCON0, #307, 0, 16, 0
	.symb	ALAB, MAIN_vWriteWDTCON0, #307
MAIN_vWriteWDTCON0:
	.symb	SOFF, 16
	.symb	LTIM, "uwValue", 4, 0, 0x8cd
	.symb	IDEN, "uwValue", 4, #18, 0, 0x80d
	.symb	IDEN, "uwDummy", -12, #18, 131, 0x5
	.symb	LTIM, "uwValue", 4, 0, 0x84d
	.symb	LTIM, "uwValue", -16, 131, 0x8c5
	nop
	sub16.a	sp,#16
;  432 |  uword uwDummy;
	.symb	LINE, 432
	st16.w	[sp],d4				; uwValue
;  433 |
;  434 |  uwDummy  =  WDT_CON0;
	.symb	LINE, 434
	ld.w	d15,-268435424
	st16.w	[sp]4,d15			; uwDummy
;  435 |  uwDummy |=  0x000000F0;       //  set HWPW1 = 1111b
	.symb	LINE, 435
	ld16.w	d15,[sp]4			; uwDummy
	or	d15,d15,#240			; uwDummy
	st16.w	[sp]4,d15			; uwDummy
;  436 |
;  437 |  if(WDT_CON1_WDTDR)
	.symb	LINE, 437
	ld.bu	d15,-268435420
	extr.u	d15,d15,#3,#1
	jeq	d15,#0,_17
;  438 |  {
;  439 |    uwDummy |=  0x00000008;     //  set HWPW0 = WDTDR
	.symb	LINE, 439
	ld16.w	d15,[sp]4			; uwDummy
	or	d15,d15,#8			; uwDummy
	st16.w	[sp]4,d15			; uwDummy
;  440 |  }
	.symb	LINE, 440
	j	_18
_17:
;  441 |  else
;  442 |  {
;  443 |    uwDummy &= ~0x00000008;     //  set HWPW0 = WDTDR
	.symb	LINE, 443
	nop
	ld16.w	d15,[sp]4			; uwDummy
	mov	d7,#-9				; -9
	and16	d15,d7				; uwDummy
	st16.w	[sp]4,d15			; uwDummy
;  444 |  }
	.symb	LINE, 444
_18:
;  445 |  if(WDT_CON1_WDTIR)
	.symb	LINE, 445
	ld.bu	d15,-268435420
	extr.u	d15,d15,#2,#1
	jeq	d15,#0,_19
;  446 |  {
;  447 |    uwDummy |=  0x00000004;     //  set HWPW0 = WDTIR
	.symb	LINE, 447
	ld16.w	d15,[sp]4			; uwDummy
	or	d15,d15,#4			; uwDummy
	st16.w	[sp]4,d15			; uwDummy
;  448 |  }
	.symb	LINE, 448
	j	_20
_19:
;  449 |  else
;  450 |  {
;  451 |    uwDummy &= ~0x00000004;     //  set HWPW0 = WDTIR
	.symb	LINE, 451
	nop
	ld16.w	d15,[sp]4			; uwDummy
	mov16	d7,#-5				; -5
	and16	d15,d7				; uwDummy
	st16.w	[sp]4,d15			; uwDummy
;  452 |  }
	.symb	LINE, 452
_20:
	.symb	LTIM, "uwValue", -16, 131, 0x845
	.symb	LTIM, "uwValue", 15, 0, 0x8cd
	.symb	LTIM, "uwValue", 15, 0, 0x84d
	.symb	LTIM, "uwValue", 15, 0, 0x8cd
	.symb	LTIM, "uwValue", 15, 0, 0x84d
	.symb	LTIM, "uwValue", -16, 131, 0x8c5
	.symb	LTIM, "uwValue", -16, 131, 0x845
	.symb	LTIM, "uwValue", 15, 0, 0x8cd
	.symb	LTIM, "uwValue", 15, 0, 0x84d
	.symb	LTIM, "uwValue", 15, 0, 0x8cd
	.symb	LTIM, "uwValue", 15, 0, 0x84d
	.symb	LTIM, "uwValue", -16, 131, 0x8c5
	.symb	LTIM, "uwValue", -16, 131, 0x845
	.symb	LTIM, "uwValue", 15, 0, 0x8cd
;  453 |
;  454 |  uwDummy &= ~0x00000002;       //  set WDTLCK = 0
	.symb	LINE, 454
	nop
	ld16.w	d15,[sp]4			; uwDummy
	mov16	d7,#-3				; -3
	and16	d15,d7				; uwDummy
	st16.w	[sp]4,d15			; uwDummy
;  455 |  WDT_CON0 =  uwDummy;          //  unlock access
	.symb	LINE, 455
	ld16.w	d15,[sp]4			; uwDummy
	st.w	-268435424,d15
;  456 |
;  457 |  uwValue  |=  0x000000F2;      //  set HWPW1 = 1111b and WDTLCK = 1
	.symb	LINE, 457
	ld16.w	d15,[sp]			; uwValue
	or	d15,d15,#242			; uwValue
	st16.w	[sp],d15			; uwValue
;  458 |  uwValue  &= ~0x0000000C;      //  set HWPW0 = 00b
	.symb	LINE, 458
	ld16.w	d15,[sp]			; uwValue
	mov	d7,#-13				; -13
	and16	d15,d7				; uwValue
	st16.w	[sp],d15			; uwValue
;  459 |  WDT_CON0  =  uwValue;         //  write access and lock
	.symb	LINE, 459
	ld16.w	d15,[sp]			; uwValue
	st.w	-268435424,d15
;  460 |
;  461 |} //  End of function MAIN_vWriteWDTCON0
	.symb	LINE, 461
	ret16
	.symb	LTIM, "uwValue", 15, 0, 0x84d
	.symb	EFUN
;  462 |
;  463 |
;  464 |//****************************************************************************
;  465 |// @Function      void main(void) 
;  466 |//
;  467 |//----------------------------------------------------------------------------
;  468 |// @Description   This is the main function.
;  469 |//
;  470 |//----------------------------------------------------------------------------
;  471 |// @Returnvalue   None
;  472 |//
;  473 |//----------------------------------------------------------------------------
;  474 |// @Parameters    None
;  475 |//
;  476 |//----------------------------------------------------------------------------
;  477 |// @Date          12.06.2002
;  478 |//
;  479 |//****************************************************************************
;  480 |
;  481 |// USER CODE BEGIN (Main,1)
;  482 |
;  483 |// USER CODE END
;  484 |
;  485 |void main(void)
;  486 |{
	.symb	LINE, 486
	.symb	TYPE, 308, 'X', 8, #1, 26, 0
	.symb	GFUN, "main", main, #308, 0, 0, 0
	.symb	ALAB, main, #308
main:
	.symb	SOFF, 0
;  487 |  // USER CODE BEGIN (Main,2)
;  488 |
;  489 |  // USER CODE END
;  490 |
;  491 |  switch(RESET_INDICATOR)
	.symb	LINE, 491
	ld.w	d15,-268435436
	movh	d7,#0xff00			; -16777216
	and16	d15,d7
	sh	d15,d15,#-24
	addi	d15,d15,#-16
	jeq	d15,#-8,_25			; case 8
	jeq	d15,#0,_24			; case 16
	addi	d15,d15,#-16
	jeq	d15,#0,_23			; case 32
	addi	d15,d15,#-32
	jeq	d15,#0,_22			; case 64
	addi	d15,d15,#-64
	jeq	d15,#0,_21			; case 128
	j	_26				; default
;  492 |  {
;  493 |    case DEEPSLEEP_WAKEUP:       //  the last reset was an external triggered
	.symb	LINE, 493
_21:
;  494 |                                 //  hardware reset in deep sleep mode 
;  495 |                                 //  (wake-up reset)
;  496 |
;  497 |         // USER CODE BEGIN (Main,3)
;  498 |
;  499 |         // USER CODE END
;  500 |
;  501 |    case WATCHDOG_RESET:         //  the last reset was a watchdog triggered
	.symb	LINE, 501
_22:
;  502 |                                 //  (hardware) reset
;  503 |
;  504 |         // USER CODE BEGIN (Main,4)
;  505 |
;  506 |         // USER CODE END
;  507 |
;  508 |    case SOFTWARE_RESET:         //  the last reset was an internally 
	.symb	LINE, 508
_23:
;  509 |                                 //  triggered software reset
;  510 |
;  511 |         // USER CODE BEGIN (Main,5)
;  512 |
;  513 |         // USER CODE END
;  514 |
;  515 |    case HARDWARE_RESET:         //  the last reset was an externally
	.symb	LINE, 515
_24:
;  516 |                                 //  triggered hardware reset (#HRST pin)
;  517 |
;  518 |         // USER CODE BEGIN (Main,6)
;  519 |
;  520 |         // USER CODE END
;  521 |
;  522 |    case POWERON_RESET:          //  the last reset was an externally
	.symb	LINE, 522
_25:
;  523 |                                 //  triggered power on reset (#POR pin)
;  524 |
;  525 |         // USER CODE BEGIN (Main,7)
;  526 |
;  527 |         // USER CODE END
;  528 |
;  529 |    default:
	.symb	LINE, 529
_26:
;  530 |
;  531 |         // USER CODE BEGIN (Main,8)
;  532 |
;  533 |         // USER CODE END
;  534 |
;  535 |         MAIN_vInit();
	.symb	LINE, 535
	callg	MAIN_vInit
;  536 |  }
	.symb	LINE, 536
_27:
;  537 |
;  538 |
;  539 |  // USER CODE BEGIN (Main,9)
;  540 |
;  541 |/*  
;  542 |IO_vSetPinOut(IO_P10_10);
;  543 |IO_vSetPinIn(IO_P10_11);
;  544 |
;  545 |while(1)
;  546 |{
;  547 | if (IO_ubReadPin(IO_P10_11))
;  548 |	IO_vSetPin(IO_P10_10);
;  549 | else
;  550 |	IO_vResetPin(IO_P10_10);
;  551 |}
;  552 |
;  553 |*/
;  554 |
;  555 |test(); 
	.symb	LINE, 555
	callg	test
;  556 |  // USER CODE END
;  557 |
;  558 |} //  End of function main
	.symb	LINE, 558
	ret16
	.symb	EFUN
;  559 |
;  560 |
;  561 |
;  562 |// USER CODE BEGIN (MAIN_General,10)
;  563 |
;  564 |// USER CODE END
;  565 |
	.symb	ENDF
	.symb	TYPE, 309, 'X', 8, #1, 26, 0
	.symb	ALAB, ASC0_vInit, #309
	.symb	TYPE, 310, 'X', 8, #1, 26, 0
	.symb	ALAB, CAN_vInit, #310
	.symb	TYPE, 311, 'X', 8, #1, 26, 0
	.symb	ALAB, ASC1_vInit, #311
	.symb	IDEN, "ucErrorFlag", ucErrorFlag, #3, 131, 0x0
	.symb	ALAB, ucErrorFlag, #3
	.sdecl	"bss.main",DATA,CLEAR,ABS18
	.sect	"bss.main"
	.align	4
ucErrorFlag:
	.space	1
	.symb	TYPE, 312, 'X', 8, #1, 26, 0
	.symb	ALAB, IO_vInit, #312
	.symb	TYPE, 313, 'X', 8, #1, 26, 0
	.symb	ALAB, test, #313
	.symb	IDEN, "uiPRG_Offset", uiPRG_Offset, #18, 131, 0x0
	.symb	ALAB, uiPRG_Offset, #18
	.align	2
uiPRG_Offset:
	.space	4
	.align	4
	.global	MAIN_vInit
	.global	MAIN_vWriteWDTCON0
	.global	main
	.global	ucErrorFlag
	.global	uiPRG_Offset
	.extern	(CODE) ASC0_vInit
	.extern	(CODE) ASC1_vInit
	.extern	(CODE) CAN_vInit
	.extern	(CODE) IO_vInit
	.extern	_START
	.extern	(DATA) _lc_ub_xvwbuffer
	.extern	(DATA) _lc_ue_xvwbuffer
	.extern	(CODE) test
	.calls	"MAIN_vInit", "ASC0_vInit"
	.calls	"MAIN_vInit", "ASC1_vInit"
	.calls	"MAIN_vInit", "CAN_vInit"
	.calls	"MAIN_vInit", "IO_vInit"
	.calls	"MAIN_vInit", "MAIN_vWriteWDTCON0"
	.calls	"main", "MAIN_vInit"
	.calls	"main", "test"
