; TASKING TriCore C compiler v1.5r1 Build 322 SN 00090364
; options: -e -A1 -g -O1 -Id:\ctri\include -s -N8 -zTC112_COR1 -zTC112_COR4
;          -zTC112_COR10 -zTC112_COR13 -zTC112_COR14 -zTC112_COR16 -zTC112_COR17
	.name	"main"
	.symb	TOOL, "TASKING TriCore C compiler v1.5", 1
	.symb	TYPE, 256, "bit", 'g', 0, 1
	.symb	FILE, "main.c"
; file "main.c":
;    1 |//****************************************************************************
;    2 |// @Module        Project Settings
;    3 |// @Filename      MAIN.C
;    4 |// @Project       eWebDemo.dav
;    5 |//----------------------------------------------------------------------------
;    6 |// @Controller    Infineon TC1775 B-Step
;    7 |//
;    8 |// @Compiler      Tasking
;    9 |//
;   10 |// @Codegenerator 2.2
;   11 |//
;   12 |// @Description   This file contains the project initialization function.
;   13 |//
;   14 |//----------------------------------------------------------------------------
;   15 |// @Date          20.06.2002 14:16:14
;   16 |//
;   17 |//****************************************************************************
;   18 |
;   19 |// USER CODE BEGIN (MAIN_General,1)
;   20 |
;   21 |// USER CODE END
;   22 |
;   23 |
;   24 |
;   25 |//****************************************************************************
;   26 |// @Project Includes
;   27 |//****************************************************************************
;   28 |
;   29 |#include "MAIN.H"
	.symb	FILE, "MAIN.H"
	.symb	TYPE, 257, "uword", 'T', #18
	.symb	FILE, "TC1775BRegs.h"
	.symb	ENDF
	.symb	FILE, "GPTU.H"
	.symb	ENDF
	.symb	FILE, "RTC.H"
	.symb	ENDF
	.symb	ENDF
;   30 |
;   31 |// USER CODE BEGIN (MAIN_General,2)
;   32 |
;   33 |// USER CODE END
;   34 |
;   35 |
;   36 |//****************************************************************************
;   37 |// @Macros
;   38 |//****************************************************************************
;   39 |
;   40 |// USER CODE BEGIN (MAIN_General,3)
;   41 |
;   42 |// USER CODE END
;   43 |
;   44 |
;   45 |//****************************************************************************
;   46 |// @Defines
;   47 |//****************************************************************************
;   48 |
;   49 |#define RESET_INDICATOR     ((RST_SR & 0xFF000000) >> 24)
;   50 |#define DEEPSLEEP_WAKEUP    0x80
;   51 |#define WATCHDOG_RESET      0x40
;   52 |#define SOFTWARE_RESET      0x20
;   53 |#define HARDWARE_RESET      0x10
;   54 |#define POWERON_RESET       0x08
;   55 |
;   56 |// USER CODE BEGIN (MAIN_General,4)
;   57 |#define OSZ_FREQUENCY 16 // external oszilator frequency in MHz
;   58 |// USER CODE END
;   59 |
;   60 |
;   61 |//****************************************************************************
;   62 |// @Typedefs
;   63 |//****************************************************************************
;   64 |
;   65 |// USER CODE BEGIN (MAIN_General,5)
;   66 |
;   67 |// USER CODE END
;   68 |
;   69 |
;   70 |//****************************************************************************
;   71 |// @Imported Global Variables
;   72 |//****************************************************************************
;   73 |
;   74 |// USER CODE BEGIN (MAIN_General,6)
;   75 |
;   76 |// USER CODE END
;   77 |
;   78 |
;   79 |//****************************************************************************
;   80 |// @Global Variables
;   81 |//****************************************************************************
;   82 |
;   83 |// USER CODE BEGIN (MAIN_General,7)
;   84 |
;   85 |// USER CODE END
;   86 |
;   87 |
;   88 |//****************************************************************************
;   89 |// @External Prototypes
;   90 |//****************************************************************************
;   91 |
;   92 |// USER CODE BEGIN (MAIN_General,8)
;   93 |
;   94 |// USER CODE END
;   95 |
;   96 |
;   97 |//****************************************************************************
;   98 |// @Prototypes Of Local Functions
;   99 |//****************************************************************************
;  100 |
;  101 |// USER CODE BEGIN (MAIN_General,9)
;  102 |extern void easyweb (void);
;  103 |// USER CODE END
;  104 |
;  105 |
;  106 |//****************************************************************************
;  107 |// @Function      void MAIN_vInit(void) 
;  108 |//
;  109 |//----------------------------------------------------------------------------
;  110 |// @Description   This function initializes the microcontroller.
;  111 |//
;  112 |//----------------------------------------------------------------------------
;  113 |// @Returnvalue   None
;  114 |//
;  115 |//----------------------------------------------------------------------------
;  116 |// @Parameters    None
;  117 |//
;  118 |//----------------------------------------------------------------------------
;  119 |// @Date          20.06.2002
;  120 |//
;  121 |//****************************************************************************
;  122 |
;  123 |// USER CODE BEGIN (Init,1)
;  124 |
;  125 |// USER CODE END
;  126 |
;  127 |void MAIN_vInit(void)
;  128 |{
	.sdecl	"code.main",CODE
	.sect	"code.main"
	.align	4
	.symb	LINE, 128
	.symb	TYPE, 258, 'X', 8, #1, 26, 0
	.symb	GFUN, "MAIN_vInit", MAIN_vInit, #258, 0, 0, 0
	.symb	ALAB, MAIN_vInit, #258
MAIN_vInit:
	mov16	d15,#-2				; -2
	.symb	SOFF, 0
;  129 |  // USER CODE BEGIN (Init,2)
;  130 |
;  131 |  // USER CODE END
;  132 |
;  133 |  //// -----------------------------------------------------------------------
;  134 |  //// Begin of Important Settings for the Start-Up File
;  135 |  //// -----------------------------------------------------------------------
;  136 |  ///  All following settings must be set in the start-up file. You can use 
;  137 |  ///  DAvE's project file (*.dpt) to include this register values into your 
;  138 |  ///  compiler EDE.
;  139 |
;  140 |    ///  ---------------------------------------------------------------------
;  141 |    ///  Bus Control Unit (BCU):
;  142 |    ///  ---------------------------------------------------------------------
;  143 |    ///  BCU starvation protection is enabled
;  144 |    ///  BCU power saving is disabled
;  145 |    ///  the debug trace is enabled. Error information is captured in 
;  146 |    ///  register BCEADD, BCEDAT and BCECON
;  147 |    ///  sample period of request for starvation protection: 64
;  148 |    ///  BCU bus time-out value: 65536 cycles
;  149 |
;  150 |    //// this register must be set in the start-up file
;  151 |    //// BCU_CON  =  0x4009FFFF;
;  152 |
;  153 |    ///  ---------------------------------------------------------------------
;  154 |    ///  Program Memory Unit (PMU):
;  155 |    ///  ---------------------------------------------------------------------
;  156 |    ///  ICACHE settings:
;  157 |    ///  the instruction cache is enabled
;  158 |    ///  the instruction cache is bypassed
;  159 |
;  160 |    //// this register must be set in the start-up file
;  161 |    //// PMU_CON  =  0x04000706;
;  162 |
;  163 |    ///  external flash settings:
;  164 |    ///  min. wait cycles between consecutive burst accesses from external 
;  165 |    ///  Flash: 0 wait cycles
;  166 |    ///  read wait cycles between the initial address and the first data 
;  167 |    ///  cycle: 0 wait cycles
;  168 |    ///  two address cycles
;  169 |    ///  two data cycles
;  170 |    ///  unlimeted numbers of linear Flash burst data cycles
;  171 |    ///  max. number of burst data cycle: 1 data accesses
;  172 |    ///  #WAIT input operates as a wait data bus function on bursts
;  173 |    ///  #CS0 is activated during burst mode
;  174 |
;  175 |    //// this register must be set in the start-up file
;  176 |    //// PMU_EIFCON  =  0x00000051;
;  177 |
;  178 |    ///  ---------------------------------------------------------------------
;  179 |    ///  External Bus Unit (EBU):
;  180 |    ///  ---------------------------------------------------------------------
;  181 |
;  182 |    ///  enable the EBU module
;  183 |
;  184 |    //// this register must be set in the start-up file
;  185 |    //// EBU_CLC  =  0x00000000;
;  186 |
;  187 |    ///  External Arbitration:
;  188 |    ///  EBU is external master
;  189 |    ///  arbitration inputs are asynchronous
;  190 |    ///  external bus will not be locked after EBU gained ownership
;  191 |    ///  enable external accesses to FPI bus
;  192 |    ///  disable external address extension register reconfiguration
;  193 |    ///  all accesses from external master are performed in user mode
;  194 |    ///  disable Time-out
;  195 |    ///  chip select triggered driver turn-around inactive cycles: 0
;  196 |    ///  read-write triggered driver turn-around inactive cycles: 0
;  197 |
;  198 |    //// this register must be set in the start-up file
;  199 |    //// EBU_CON  =  0x00000068;
;  200 |
;  201 |    ///  Overlay Memory:
;  202 |    ///  do not activate chip select #CSOVL on an access to memory region 0
;  203 |    ///  do not activate chip select #CSOVL on an access to memory region 1
;  204 |    ///  do not activate chip select #CSOVL on an access to memory region 2
;  205 |    ///  do not activate chip select #CSOVL on an access to memory region 3
;  206 |
;  207 |    //// this register must be set in the start-up file
;  208 |    //// EBU_EMUCON  =  0x00000000;
;  209 |
;  210 |    ///  Address Region 0:
;  211 |    ///  enable memory region 0
;  212 |    ///  length of the region: 4 Mbyte
;  213 |    ///  relevant start address (A31 : A0): 0xB0000000
;  214 |    ///  writes to memory region are enabled
;  215 |    ///  address generation: demuxed address mode
;  216 |    ///  external device data width: 32-bit
;  217 |    ///  address latch enable (ALE) duration: 3 cycles
;  218 |    ///  byte control signal timing mode: chipselect mode
;  219 |    ///  cycle 0 is not generated
;  220 |    ///  variable waitstate insertion is disabled
;  221 |    ///  pin #WAIT is low active
;  222 |    ///  read cycle multiplier is 1
;  223 |    ///  read access waitstates: 48
;  224 |    ///  cycle multiplier is 16
;  225 |    ///  write access waitstates: 112
;  226 |    ///  hold/pause cycle waitstates: 48
;  227 |    ///  recovery cycles waitstates: 48
;  228 |
;  229 |    //// this register must be set in the start-up file
;  230 |    //// EBU_ADDSEL0  =  0xB0000051;
;  231 |    //// EBU_BUSCON0  =  0x600261FF;
;  232 |
;  233 |    ///  Address Region 1:
;  234 |    ///  enable memory region 1
;  235 |    ///  length of the region: 1 Mbyte
;  236 |    ///  relevant start address (A31 : A0): 0xA0000000
;  237 |    ///  writes to memory region are enabled
;  238 |    ///  address generation: demuxed address mode
;  239 |    ///  external device data width: 32-bit
;  240 |    ///  address latch enable (ALE) duration: 3 cycles
;  241 |    ///  byte control signal timing mode: chipselect mode
;  242 |    ///  cycle 0 is not generated
;  243 |    ///  variable waitstate insertion is disabled
;  244 |    ///  pin #WAIT is low active
;  245 |    ///  read cycle multiplier is 1
;  246 |    ///  read access waitstates: 48
;  247 |    ///  cycle multiplier is 16
;  248 |    ///  write access waitstates: 112
;  249 |    ///  hold/pause cycle waitstates: 48
;  250 |    ///  recovery cycles waitstates: 48
;  251 |
;  252 |    //// this register must be set in the start-up file
;  253 |    //// EBU_ADDSEL1  =  0xA0000071;
;  254 |    //// EBU_BUSCON1  =  0x600261FF;
;  255 |
;  256 |    ///  Address Region 2:
;  257 |    ///  enable memory region 2
;  258 |    ///  length of the region: 1 Mbyte
;  259 |    ///  relevant start address (A31 : A0): 0xA0100000
;  260 |    ///  writes to memory region are enabled
;  261 |    ///  address generation: demuxed address mode
;  262 |    ///  external device data width: 32-bit
;  263 |    ///  address latch enable (ALE) duration: 3 cycles
;  264 |    ///  byte control signal timing mode: chipselect mode
;  265 |    ///  cycle 0 is not generated
;  266 |    ///  variable waitstate insertion is disabled
;  267 |    ///  pin #WAIT is low active
;  268 |    ///  read cycle multiplier is 1
;  269 |    ///  read access waitstates: 48
;  270 |    ///  cycle multiplier is 16
;  271 |    ///  write access waitstates: 112
;  272 |    ///  hold/pause cycle waitstates: 48
;  273 |    ///  recovery cycles waitstates: 48
;  274 |
;  275 |    //// this register must be set in the start-up file
;  276 |    //// EBU_ADDSEL2  =  0xA0100071;
;  277 |    //// EBU_BUSCON2  =  0x600261FF;
;  278 |
;  279 |    ///  Address Region 3:
;  280 |    ///  enable memory region 3
;  281 |    ///  length of the region: 128 Mbyte
;  282 |    ///  relevant start address (A31 : A0): 0xA0000000
;  283 |    ///  writes to memory region are disabled
;  284 |    ///  address generation: demuxed address mode
;  285 |    ///  external device data width: 32-bit
;  286 |    ///  address latch enable (ALE) duration: 3 cycles
;  287 |    ///  byte control signal timing mode: control mode
;  288 |    ///  cycle 0 is not generated
;  289 |    ///  variable waitstate insertion is disabled
;  290 |    ///  pin #WAIT is low active
;  291 |    ///  read cycle multiplier is 1
;  292 |    ///  read access waitstates: 48
;  293 |    ///  cycle multiplier is 16
;  294 |    ///  write access waitstates: 112
;  295 |    ///  hold/pause cycle waitstates: 48
;  296 |    ///  recovery cycles waitstates: 48
;  297 |
;  298 |    //// this register must be set in the start-up file
;  299 |    //// EBU_ADDSEL3  =  0xA0000001;
;  300 |    //// EBU_BUSCON3  =  0xE80261FF;
;  301 |
;  302 |    ///  Emulator Address Region :
;  303 |    ///  enable emulator memory region
;  304 |    ///  length of the region: 16 Mbyte
;  305 |    ///  relevant start address (A31 : A0): 0xBE000000
;  306 |    ///  writes to memory region are enabled
;  307 |    ///  address generation: demuxed address mode
;  308 |    ///  external device data width: 32-bit
;  309 |    ///  address latch enable (ALE) duration: 0 cycles
;  310 |    ///  byte control signal timing mode: chipselect mode
;  311 |    ///  cycle 0 is generated
;  312 |    ///  asynchronous waitstate insertion
;  313 |    ///  pin #WAIT is low active
;  314 |    ///  read cycle multiplier is 1
;  315 |    ///  read access waitstates: 1
;  316 |    ///  cycle multiplier is 1
;  317 |    ///  write access waitstates: 2
;  318 |    ///  hold/pause cycle waitstates: 0
;  319 |    ///  recovery cycles waitstates: 0
;  320 |
;  321 |    //// this register must be set in the start-up file
;  322 |    //// EBU_EMUAS  =  0xBE000031;
;  323 |    //// EBU_EMUBC  =  0x00160280;
;  324 |
;  325 |  //// -----------------------------------------------------------------------
;  326 |  //// End of Important Settings for the Start-Up File
;  327 |  //// -----------------------------------------------------------------------
;  328 |
;  329 |  ///  -----------------------------------------------------------------------
;  330 |  ///  Clock System:
;  331 |  ///  -----------------------------------------------------------------------
;  332 |  ///  - external clock frequency: 16,000 MHz
;  333 |  ///  - PLL operation (pin BYPASS = 0)
;  334 |  ///  - clock factor (N-factor): 10 (pins CLKSEL[2:0] = 0x2)
;  335 |  ///  - VCO output frequency: 160,000 MHz
;  336 |  ///  - clock divider (K-factor): 4
;  337 |  ///  - system clock: 40,000 MHz
;  338 |
;  339 |  MAIN_vResetENDINIT();
	.symb	LINE, 339
	ld.w	d4,-268435424
	and16	d4,d15
	callg	MAIN_vWriteWDTCON0
;  340 |  PLL_CLC        =  0x00020000;  // load PLL clock control register
	.symb	LINE, 340
	movh	d15,#0x2
	st.w	-268435392,d15
;  341 |  MAIN_vSetENDINIT();
	.symb	LINE, 341
	ld.w	d4,-268435424
	or	d4,d4,#1
	callg	MAIN_vWriteWDTCON0
;  342 |
;  343 |  ///  -----------------------------------------------------------------------
;  344 |  ///  Interrupt System:
;  345 |  ///  -----------------------------------------------------------------------
;  346 |  ///  - four arbitration cycles (max. 255 interrupt sources)
;  347 |  ///  - two clocks per arbitration cycle
;  348 |
;  349 |  MTCR(0xFE2C,  0x00000000);     // load CPU interrupt control register
	.symb	LINE, 349
	mov16	d15,#0				; 0
	mtcr	#65068,d15			; 65068
;  350 |  ISYNC();
	.symb	LINE, 350
	isync
	mov16	d15,#-2				; -2
;  351 |
;  352 |  ///  -----------------------------------------------------------------------
;  353 |  ///  Peripheral Control Processor (PCP):
;  354 |  ///  -----------------------------------------------------------------------
;  355 |  ///  - four arbitration cycles (max. 255 PCP channels)
;  356 |  ///  - two clocks per arbitration cycle
;  357 |  ///  - use Full Context save area (R[0] - R[7])
;  358 |  ///  - channel start at context PC
;  359 |  ///  - the PCP error interrupt is disabled
;  360 |  ///  - PRAM partitioning is disabled
;  361 |  ///  - channel watchdog is disabled
;  362 |
;  363 |  MAIN_vResetENDINIT();
	.symb	LINE, 363
	ld.w	d4,-268435424
	and16	d4,d15
	callg	MAIN_vWriteWDTCON0
;  364 |  PCP_CS         =  0x00020800;  // load PCP control and status register
	.symb	LINE, 364
	mov.u	d15,#0x800
	addih	d15,d15,#0x2
	st.w	-268419312,d15
;  365 |  MAIN_vSetENDINIT();
	.symb	LINE, 365
	ld.w	d4,-268435424
	or	d4,d4,#1
	callg	MAIN_vWriteWDTCON0
;  366 |
;  367 |  PCP_ICR        =  0x00000000;  // load PCP interrupt control register
	.symb	LINE, 367
	mov16	d15,#0
	st.w	-268419296,d15
;  368 |
;  369 |  //   -----------------------------------------------------------------------
;  370 |  //   Initialization of the Peripherals:
;  371 |  //   -----------------------------------------------------------------------
;  372 |  //   initializes the General Purpose Timer Unit (GPTU)
;  373 |  GPTU_vInit();
	.symb	LINE, 373
	callg	GPTU_vInit
;  374 |
;  375 |  //   initializes the Real Time Clock (RTC)
;  376 |  RTC_vInit();
	.symb	LINE, 376
	callg	RTC_vInit
;  377 |
;  378 |
;  379 |  // USER CODE BEGIN (Init,3)
;  380 |
;  381 |  // USER CODE END
;  382 |
;  383 |  ///  -----------------------------------------------------------------------
;  384 |  ///  System Start Conditions:
;  385 |  ///  -----------------------------------------------------------------------
;  386 |
;  387 |  ///  - the CPU interrupt system is globally enabled
;  388 |  ENABLE();
	.symb	LINE, 388
	enable
;  389 |
;  390 |  //// - the PCP interrupt system is globally disabled
;  391 |
;  392 |
;  393 |  // USER CODE BEGIN (Init,4)
;  394 |
;  395 |  // USER CODE END
;  396 |
;  397 |} //  End of function MAIN_vInit
	.symb	LINE, 397
	ret16
	.symb	EFUN
;  398 |
;  399 |
;  400 |//****************************************************************************
;  401 |// @Function      void MAIN_vWriteWDTCON0(uword uwValue) 
;  402 |//
;  403 |//----------------------------------------------------------------------------
;  404 |// @Description   This function writes the parameter uwValue to the WDT_CON0 
;  405 |//                register which is password protected. 
;  406 |//
;  407 |//----------------------------------------------------------------------------
;  408 |// @Returnvalue   None
;  409 |//
;  410 |//----------------------------------------------------------------------------
;  411 |// @Parameters    uwValue: 
;  412 |//                Value for the WDTCON0 register
;  413 |//
;  414 |//----------------------------------------------------------------------------
;  415 |// @Date          20.06.2002
;  416 |//
;  417 |//****************************************************************************
;  418 |
;  419 |// USER CODE BEGIN (WriteWDTCON0,1)
;  420 |
;  421 |// USER CODE END
;  422 |
;  423 |void MAIN_vWriteWDTCON0(uword uwValue)
;  424 |{
	.symb	LINE, 424
	.symb	TYPE, 259, 'g', 0, 1
	.symb	TYPE, 260, 'g', 0, 1
	.symb	TYPE, 261, 'g', 0, 1
	.symb	TYPE, 262, 'g', 0, 1
	.symb	TYPE, 263, 'g', 0, 1
	.symb	TYPE, 264, 'g', 0, 1
	.symb	TYPE, 265, 'g', 0, 1
	.symb	TYPE, 266, 'g', 0, 1
	.symb	TYPE, 267, 'g', 0, 1
	.symb	TYPE, 268, 'g', 0, 1
	.symb	TYPE, 269, 'g', 0, 1
	.symb	TYPE, 270, 'g', 0, 1
	.symb	TYPE, 271, 'g', 0, 1
	.symb	TYPE, 272, 'g', 0, 1
	.symb	TYPE, 273, 'g', 0, 1
	.symb	TYPE, 274, 'g', 0, 1
	.symb	TYPE, 275, 'g', 0, 1
	.symb	TYPE, 276, 'g', 0, 1
	.symb	TYPE, 277, 'g', 0, 1
	.symb	TYPE, 278, 'g', 0, 1
	.symb	TYPE, 279, 'g', 0, 1
	.symb	TYPE, 280, 'g', 0, 1
	.symb	TYPE, 281, 'g', 0, 1
	.symb	TYPE, 282, 'g', 0, 1
	.symb	TYPE, 283, 'g', 0, 1
	.symb	TYPE, 284, 'g', 0, 1
	.symb	TYPE, 285, 'g', 0, 1
	.symb	TYPE, 286, 'g', 0, 1
	.symb	TYPE, 287, 'g', 0, 1
	.symb	TYPE, 288, 'g', 0, 1
	.symb	TYPE, 289, 'g', 0, 1
	.symb	TYPE, 290, 'g', 0, 1
	.symb	TYPE, 291, 'S', 4,\
		 "bit0", #259, 0,\
		 "bit1", #260, 1,\
		 "bit2", #261, 2,\
		 "bit3", #262, 3,\
		 "bit4", #263, 4,\
		 "bit5", #264, 5,\
		 "bit6", #265, 6,\
		 "bit7", #266, 7,\
		 "bit8", #267, 8,\
		 "bit9", #268, 9,\
		 "bit10", #269, 10,\
		 "bit11", #270, 11,\
		 "bit12", #271, 12,\
		 "bit13", #272, 13,\
		 "bit14", #273, 14,\
		 "bit15", #274, 15,\
		 "bit16", #275, 16,\
		 "bit17", #276, 17,\
		 "bit18", #277, 18,\
		 "bit19", #278, 19,\
		 "bit20", #279, 20,\
		 "bit21", #280, 21,\
		 "bit22", #281, 22,\
		 "bit23", #282, 23,\
		 "bit24", #283, 24,\
		 "bit25", #284, 25,\
		 "bit26", #285, 26,\
		 "bit27", #286, 27,\
		 "bit28", #287, 28,\
		 "bit29", #288, 29,\
		 "bit30", #289, 30,\
		 "bit31", #290, 31
	.symb	TYPE, 292, "T_Reg32", 'T', #291
	.symb	TYPE, 293, 'X', 8, #1, 26, 1, #18
	.symb	GFUN, "MAIN_vWriteWDTCON0", MAIN_vWriteWDTCON0, #293, 0, 0, 0
	.symb	ALAB, MAIN_vWriteWDTCON0, #293
MAIN_vWriteWDTCON0:
	.symb	IDEN, "uwValue", 4, #18, 0, 0x80d
	.symb	IDEN, "uwDummy", -1, #18, 131, 0x5
	.symb	SOFF, 0
	.symb	LTIM, "uwValue", 4, 0, 0x8cd
	.symb	LTIM, "uwDummy", -1, 0, 0x45
	.symb	LTIM, "uwDummy", 15, 0, 0xcd
	.symb	LTIM, "uwDummy", 15, 0, 0x4d
	.symb	LTIM, "uwDummy", 15, 0, 0xcd
	.symb	LTIM, "uwDummy", 15, 0, 0x4d
	.symb	LTIM, "uwDummy", 15, 0, 0xcd
	.symb	LTIM, "uwDummy", 15, 0, 0x4d
	.symb	LTIM, "uwDummy", 15, 0, 0xcd
	.symb	LTIM, "uwDummy", 15, 0, 0x4d
	.symb	LTIM, "uwDummy", 15, 0, 0xcd
;  425 |  uword uwDummy;
;  426 |
;  427 |  uwDummy  =  WDT_CON0;
	.symb	LINE, 427
	ld.w	d15,-268435424
;  428 |  uwDummy |=  0x000000F0;       //  set HWPW1 = 1111b
	.symb	LINE, 428
	or	d15,d15,#240			; uwDummy
;  429 |
;  430 |  if(WDT_CON1_WDTDR)
	.symb	LINE, 430
	ld.bu	d7,-268435420
	jz.t	d7:3,_3
;  431 |  {
;  432 |    uwDummy |=  0x00000008;     //  set HWPW0 = WDTDR
	.symb	LINE, 432
	or	d15,d15,#8			; uwDummy
;  433 |  }
	.symb	LINE, 433
	j	_4
_3:
	.symb	LTIM, "uwDummy", 15, 0, 0x4d
	.symb	LTIM, "uwDummy", 15, 0, 0xcd
	.symb	LTIM, "uwDummy", 15, 0, 0x4d
	.symb	LTIM, "uwDummy", 15, 0, 0xcd
;  434 |  else
;  435 |  {
;  436 |    uwDummy &= ~0x00000008;     //  set HWPW0 = WDTDR
	.symb	LINE, 436
	mov	d7,#-9				; -9
	and16	d15,d7				; uwDummy
;  437 |  }
	.symb	LINE, 437
_4:
	.symb	LTIM, "uwDummy", 15, 0, 0x4d
	.symb	LTIM, "uwDummy", 15, 0, 0xcd
	.symb	LTIM, "uwDummy", 15, 0, 0x4d
	.symb	LTIM, "uwDummy", 15, 0, 0xcd
;  438 |  if(WDT_CON1_WDTIR)
	.symb	LINE, 438
	ld.bu	d7,-268435420
	jz.t	d7:2,_5
;  439 |  {
;  440 |    uwDummy |=  0x00000004;     //  set HWPW0 = WDTIR
	.symb	LINE, 440
	or	d15,d15,#4			; uwDummy
;  441 |  }
	.symb	LINE, 441
	j	_6
_5:
	.symb	LTIM, "uwDummy", 15, 0, 0x4d
	.symb	LTIM, "uwDummy", 15, 0, 0xcd
	.symb	LTIM, "uwDummy", 15, 0, 0x4d
	.symb	LTIM, "uwDummy", 15, 0, 0xcd
;  442 |  else
;  443 |  {
;  444 |    uwDummy &= ~0x00000004;     //  set HWPW0 = WDTIR
	.symb	LINE, 444
	mov16	d7,#-5				; -5
	and16	d15,d7				; uwDummy
;  445 |  }
	.symb	LINE, 445
_6:
	.symb	LTIM, "uwDummy", 15, 0, 0x4d
	.symb	LTIM, "uwDummy", 15, 0, 0xcd
	.symb	LTIM, "uwDummy", 15, 0, 0x4d
	.symb	LTIM, "uwDummy", 15, 0, 0xcd
	.symb	LTIM, "uwValue", 4, 0, 0x84d
	.symb	LTIM, "uwValue", 4, 0, 0x8cd
	.symb	LTIM, "uwValue", 4, 0, 0x84d
	.symb	LTIM, "uwValue", 4, 0, 0x8cd
	.symb	LTIM, "uwDummy", 15, 0, 0x4d
	.symb	LTIM, "uwValue", 4, 0, 0x84d
	.symb	LTIM, "uwValue", 15, 0, 0x8cd
	.symb	LTIM, "uwValue", 15, 0, 0x84d
	.symb	LTIM, "uwValue", 15, 0, 0x8cd
;  446 |
;  447 |  uwDummy &= ~0x00000002;       //  set WDTLCK = 0
	.symb	LINE, 447
	mov16	d7,#-3				; -3
	and16	d15,d7				; uwDummy
;  448 |  WDT_CON0 =  uwDummy;          //  unlock access
	.symb	LINE, 448
	st.w	-268435424,d15
;  449 |
;  450 |  uwValue  |=  0x000000F2;      //  set HWPW1 = 1111b and WDTLCK = 1
	.symb	LINE, 450
	or	d4,d4,#242			; uwValue
;  451 |  uwValue  &= ~0x0000000C;      //  set HWPW0 = 00b
	.symb	LINE, 451
	mov	d15,#-13			; -13
	and16	d15,d4				; uwValue
;  452 |  WDT_CON0  =  uwValue;         //  write access and lock
	.symb	LINE, 452
	st.w	-268435424,d15
;  453 |
;  454 |} //  End of function MAIN_vWriteWDTCON0
	.symb	LINE, 454
	ret16
	.symb	LTIM, "uwValue", 15, 0, 0x84d
	.symb	EFUN
;  455 |
;  456 |
;  457 |//****************************************************************************
;  458 |// @Function      void main(void) 
;  459 |//
;  460 |//----------------------------------------------------------------------------
;  461 |// @Description   This is the main function.
;  462 |//
;  463 |//----------------------------------------------------------------------------
;  464 |// @Returnvalue   None
;  465 |//
;  466 |//----------------------------------------------------------------------------
;  467 |// @Parameters    None
;  468 |//
;  469 |//----------------------------------------------------------------------------
;  470 |// @Date          20.06.2002
;  471 |//
;  472 |//****************************************************************************
;  473 |
;  474 |// USER CODE BEGIN (Main,1)
;  475 |unsigned int uiFrequency;
;  476 |
;  477 |// USER CODE END
;  478 |
;  479 |void main(void)
;  480 |{
	.symb	LINE, 480
	.symb	TYPE, 294, 'X', 8, #1, 26, 0
	.symb	GFUN, "main", main, #294, 0, 0, 0
	.symb	ALAB, main, #294
main:
	.symb	IDEN, "uiPLL", -1, #18, 131, 0x5
	.symb	IDEN, "uiK_Fak", -1, #18, 131, 0x5
	.symb	IDEN, "uiN_Fak", -1, #18, 131, 0x5
	.symb	SOFF, 0
	.symb	LTIM, "uiPLL", -1, 0, 0x45
	.symb	LTIM, "uiK_Fak", -1, 0, 0x45
	.symb	LTIM, "uiN_Fak", -1, 0, 0x45
	.symb	LTIM, "uiPLL", 15, 0, 0xcd
	.symb	LTIM, "uiK_Fak", 5, 0, 0xcd
	.symb	LTIM, "uiN_Fak", 4, 0, 0xcd
	.symb	LTIM, "uiK_Fak", 5, 0, 0x4d
	.symb	LTIM, "uiK_Fak", 5, 0, 0xcd
;  481 |  // USER CODE BEGIN (Main,2)
;  482 |unsigned int	uiPLL, uiK_Fak, uiN_Fak;
;  483 |  // USER CODE END
;  484 |
;  485 |  switch(RESET_INDICATOR)
	.symb	LINE, 485
	ld.w	d15,-268435436
;  486 |  {
;  487 |    case DEEPSLEEP_WAKEUP:       //  the last reset was an external triggered
;  488 |                                 //  hardware reset in deep sleep mode 
;  489 |                                 //  (wake-up reset)
;  490 |
;  491 |         // USER CODE BEGIN (Main,3)
;  492 |
;  493 |         // USER CODE END
;  494 |
;  495 |    case WATCHDOG_RESET:         //  the last reset was a watchdog triggered
;  496 |                                 //  (hardware) reset
;  497 |
;  498 |         // USER CODE BEGIN (Main,4)
;  499 |
;  500 |         // USER CODE END
;  501 |
;  502 |    case SOFTWARE_RESET:         //  the last reset was an internally 
;  503 |                                 //  triggered software reset
;  504 |
;  505 |         // USER CODE BEGIN (Main,5)
;  506 |
;  507 |         // USER CODE END
;  508 |
;  509 |    case HARDWARE_RESET:         //  the last reset was an externally
;  510 |                                 //  triggered hardware reset (#HRST pin)
;  511 |
;  512 |         // USER CODE BEGIN (Main,6)
;  513 |
;  514 |         // USER CODE END
;  515 |
;  516 |    case POWERON_RESET:          //  the last reset was an externally
;  517 |                                 //  triggered power on reset (#POR pin)
;  518 |
;  519 |         // USER CODE BEGIN (Main,7)
;  520 |
;  521 |         // USER CODE END
;  522 |
;  523 |    default:
;  524 |
;  525 |         // USER CODE BEGIN (Main,8)
;  526 |
;  527 |         // USER CODE END
;  528 |
;  529 |         MAIN_vInit();
	.symb	LINE, 529
	callg	MAIN_vInit
;  530 |  }
;  531 |
;  532 |
;  533 |  // USER CODE BEGIN (Main,9)
;  534 |
;  535 |// Set bus configuration for ethernet chip
;  536 |//EBU_BUSCON3 = 0x000107FF;    // Ethernet	16-Bit Bus	at /CS3
;  537 |
;  538 | HVAR(unsigned int,0xF000056C) = 0x60C1FFFF;	// max. wait cycles. this should 
	.symb	LINE, 538
	mov.u	d15,#0xffff
	addih	d15,d15,#0x60c1
	st.w	-268434068,d15
;  539 |												//be optimized in future
;  540 |// EBU_ADDSEL3 = 0xB0400031 ;	 //0xF000052C
;  541 | HVAR(unsigned int,0xF000052C) = 0xB0400061;	// Address for Ethernet-Chip-Select 
	.symb	LINE, 541
	mov.u	d15,#0x61
	addih	d15,d15,#0xb040
	st.w	-268434132,d15
;  542 |										//If you change it also edit the 
;  543 |											//Base-Address in file CS8900.C
;  544 |// Calculate the actual prozessor speed
;  545 |uiPLL = PLL_CLC;
	.symb	LINE, 545
	ld.w	d15,-268435392
;  546 |uiK_Fak = ((uiPLL>>16) & 0x7)+2;
	.symb	LINE, 546
	extr.u	d7,d15,#16,#3
	add16	d7,#2
	mov16	d5,d7				; uiK_Fak
;  547 |uiN_Fak = ((uiPLL>>12) & 0x7)+8;
	.symb	LINE, 547
	extr.u	d4,d15,#12,#3
	addi	d4,d4,#8
;  548 |if (uiK_Fak > 6) uiK_Fak++;
	.symb	LINE, 548
	jlt.u	d7,#7,_7
	addi	d5,d7,#1
_7:
	.symb	LTIM, "uiPLL", 15, 0, 0x4d
;  549 |if (uiPLL & 0x00008000)	 //0x00008000 = BYPASS
	.symb	LINE, 549
	mov.u	d7,#32768			; 32768
	and16	d15,d7
	jeq	d15,#0,_8
;  550 |	uiFrequency = OSZ_FREQUENCY;
	.symb	LINE, 550
	mov16	d15,#16				; uiFrequency
	st.w	uiFrequency,d15			; uiFrequency
	j	_9
_8:
	.symb	LTIM, "uiK_Fak", 5, 0, 0x4d
	.symb	LTIM, "uiK_Fak", 5, 0, 0xcd
	.symb	LTIM, "uiN_Fak", 4, 0, 0x4d
;  551 |else uiFrequency = OSZ_FREQUENCY*uiN_Fak/uiK_Fak;
	.symb	LINE, 551
	sh16	d4,#4
	callg	__rt_udivmod
	st.w	uiFrequency,d2			; uiFrequency
_9:
	.symb	LTIM, "uiK_Fak", 5, 0, 0x4d
;  552 |
;  553 |RTC_vReset();
	.symb	LINE, 553
	callg	RTC_vReset
;  554 |
;  555 |while(1)
	.symb	LINE, 555
_10:
;  556 |{
;  557 |easyweb();
	.symb	LINE, 557
	callg	easyweb
	.symb	LINE, 555
	j	_10
;  558 |}
;  559 |// USER CODE END
;  560 |
;  561 |} //  End of function main
	.symb	LINE, 561
	ret16
	.symb	EFUN
;  562 |
;  563 |
;  564 |
;  565 |// USER CODE BEGIN (MAIN_General,10)
;  566 |
;  567 |// USER CODE END
;  568 |
	.symb	ENDF
	.symb	IDEN, "uiFrequency", uiFrequency, #18, 131, 0x0
	.symb	ALAB, uiFrequency, #18
	.sdecl	"bss.main",DATA,CLEAR,ABS18
	.sect	"bss.main"
	.align	4
uiFrequency:
	.space	4
	.symb	TYPE, 295, 'X', 8, #1, 26, 0
	.symb	ALAB, easyweb, #295
	.symb	TYPE, 296, 'X', 8, #1, 26, 0
	.symb	ALAB, RTC_vInit, #296
	.symb	TYPE, 297, 'X', 8, #1, 26, 0
	.symb	ALAB, RTC_vReset, #297
	.symb	TYPE, 298, 'X', 8, #1, 26, 0
	.symb	ALAB, GPTU_vInit, #298
	.global	MAIN_vInit
	.global	MAIN_vWriteWDTCON0
	.global	main
	.global	uiFrequency
	.extern	(CODE) GPTU_vInit
	.extern	(CODE) RTC_vInit
	.extern	(CODE) RTC_vReset
	.extern	_START
	.extern	(DATA) _lc_ub_xvwbuffer
	.extern	(DATA) _lc_ue_xvwbuffer
	.extern	(CODE) easyweb
	.extern	(CODE) __rt_udivmod
	.calls	"MAIN_vInit", "GPTU_vInit"
	.calls	"MAIN_vInit", "MAIN_vWriteWDTCON0"
	.calls	"MAIN_vInit", "RTC_vInit"
	.calls	"main", "MAIN_vInit"
	.calls	"main", "RTC_vReset"
	.calls	"main", "easyweb"
