DAvE's Project Documentation

Project: 		eWebDemo.dav

Controller: 		TC1775 B-Step
Compiler: 		Tasking

Date: 			20.06.2002 14:16:17

Please read this document carefully and note
the red-colored hints.

If you miss a file in the generated files list
maybe you have forgotten to select the
initialisation function of the related module.

Generated Files:
			TC1775BREGS.H
			MAIN.H
			MAIN.C
			GPTU.H
			GPTU.C
			RTC.H
			RTC.C
			EWEBDEMO.ASM

Project Settings

Macros:

	Macro:
		MAIN_vSetENDINIT()
	Description:
		This macro sets the EndInit bit, which controls access to
		system critical registers. Setting the EndInit bit locks
		all EndInit protected registers.
	Returnvalue:
		None
	Parameters:
		None

	Macro:
		MAIN_vResetENDINIT()
	Description:
		This macro clears the EndInit bit, which controls access to
		system critical registers. Clearing the EndInit bit unlocks
		all EndInit protected registers. Modifications of the
		EndInit bit are monitored by the watchdog timer such that
		after clearing EndInit, the watchdog timer enters a defined
		time-out mode; EndInit must be set again before the
		time-out expires.
	Returnvalue:
		None
	Parameters:
		None
Functions:

	Function:
		void MAIN_vInit(void)
	Description:
		This function initializes the microcontroller.
	Returnvalue:
		None
	Parameters:
		None

	Function:
		void MAIN_vWriteWDTCON0(uword uwValue)
	Description:
		This function writes the parameter uwValue to the WDT_CON0
		register which is password protected.
	Returnvalue:
		None
	Parameters:
		uwValue:
		Value for the WDTCON0 register

	Function:
		void main(void)
	Description:
		This is the main function.
	Returnvalue:
		None
	Parameters:
		None

Initialization:

	Begin of Important Settings for the Start-Up File
	All following settings must be set in the start-up file. You can use
	DAvE's project file (*.dpt) to include this register values into your
	compiler EDE.

	Bus Control Unit (BCU):
	BCU starvation protection is enabled
	BCU power saving is disabled
	the debug trace is enabled. Error information is captured in
	register BCEADD, BCEDAT and BCECON
	sample period of request for starvation protection: 64
	BCU bus time-out value: 65536 cycles

	this register must be set in the start-up file
	BCU_CON  =  0x4009FFFF;

	Program Memory Unit (PMU):
	ICACHE settings:
	the instruction cache is enabled
	the instruction cache is bypassed

	this register must be set in the start-up file
	PMU_CON  =  0x04000706;

	external flash settings:
	min. wait cycles between consecutive burst accesses from external
	Flash: 0 wait cycles
	read wait cycles between the initial address and the first data
	cycle: 0 wait cycles
	two address cycles
	two data cycles
	unlimeted numbers of linear Flash burst data cycles
	max. number of burst data cycle: 1 data accesses
	#WAIT input operates as a wait data bus function on bursts
	#CS0 is activated during burst mode

	this register must be set in the start-up file
	PMU_EIFCON  =  0x00000051;

	External Bus Unit (EBU):

	enable the EBU module

	this register must be set in the start-up file
	EBU_CLC  =  0x00000000;

	External Arbitration:
	EBU is external master
	arbitration inputs are asynchronous
	external bus will not be locked after EBU gained ownership
	enable external accesses to FPI bus
	disable external address extension register reconfiguration
	all accesses from external master are performed in user mode
	disable Time-out
	chip select triggered driver turn-around inactive cycles: 0
	read-write triggered driver turn-around inactive cycles: 0

	this register must be set in the start-up file
	EBU_CON  =  0x00000068;

	Overlay Memory:
	do not activate chip select #CSOVL on an access to memory region 0
	do not activate chip select #CSOVL on an access to memory region 1
	do not activate chip select #CSOVL on an access to memory region 2
	do not activate chip select #CSOVL on an access to memory region 3

	this register must be set in the start-up file
	EBU_EMUCON  =  0x00000000;

	Address Region 0:
	enable memory region 0
	length of the region: 4 Mbyte
	relevant start address (A31 : A0): 0xB0000000
	writes to memory region are enabled
	address generation: demuxed address mode
	external device data width: 32-bit
	address latch enable (ALE) duration: 3 cycles
	byte control signal timing mode: chipselect mode
	cycle 0 is not generated
	variable waitstate insertion is disabled
	pin #WAIT is low active
	read cycle multiplier is 1
	read access waitstates: 48
	cycle multiplier is 16
	write access waitstates: 112
	hold/pause cycle waitstates: 48
	recovery cycles waitstates: 48

	this register must be set in the start-up file
	EBU_ADDSEL0  =  0xB0000051;
	EBU_BUSCON0  =  0x600261FF;

	Address Region 1:
	enable memory region 1
	length of the region: 1 Mbyte
	relevant start address (A31 : A0): 0xA0000000
	writes to memory region are enabled
	address generation: demuxed address mode
	external device data width: 32-bit
	address latch enable (ALE) duration: 3 cycles
	byte control signal timing mode: chipselect mode
	cycle 0 is not generated
	variable waitstate insertion is disabled
	pin #WAIT is low active
	read cycle multiplier is 1
	read access waitstates: 48
	cycle multiplier is 16
	write access waitstates: 112
	hold/pause cycle waitstates: 48
	recovery cycles waitstates: 48

	this register must be set in the start-up file
	EBU_ADDSEL1  =  0xA0000071;
	EBU_BUSCON1  =  0x600261FF;

	Address Region 2:
	enable memory region 2
	length of the region: 1 Mbyte
	relevant start address (A31 : A0): 0xA0100000
	writes to memory region are enabled
	address generation: demuxed address mode
	external device data width: 32-bit
	address latch enable (ALE) duration: 3 cycles
	byte control signal timing mode: chipselect mode
	cycle 0 is not generated
	variable waitstate insertion is disabled
	pin #WAIT is low active
	read cycle multiplier is 1
	read access waitstates: 48
	cycle multiplier is 16
	write access waitstates: 112
	hold/pause cycle waitstates: 48
	recovery cycles waitstates: 48

	this register must be set in the start-up file
	EBU_ADDSEL2  =  0xA0100071;
	EBU_BUSCON2  =  0x600261FF;

	Address Region 3:
	enable memory region 3
	length of the region: 128 Mbyte
	relevant start address (A31 : A0): 0xA0000000
	writes to memory region are disabled
	address generation: demuxed address mode
	external device data width: 32-bit
	address latch enable (ALE) duration: 3 cycles
	byte control signal timing mode: control mode
	cycle 0 is not generated
	variable waitstate insertion is disabled
	pin #WAIT is low active
	read cycle multiplier is 1
	read access waitstates: 48
	cycle multiplier is 16
	write access waitstates: 112
	hold/pause cycle waitstates: 48
	recovery cycles waitstates: 48

	this register must be set in the start-up file
	EBU_ADDSEL3  =  0xA0000001;
	EBU_BUSCON3  =  0xE80261FF;

	Emulator Address Region :
	enable emulator memory region
	length of the region: 16 Mbyte
	relevant start address (A31 : A0): 0xBE000000
	writes to memory region are enabled
	address generation: demuxed address mode
	external device data width: 32-bit
	address latch enable (ALE) duration: 0 cycles
	byte control signal timing mode: chipselect mode
	cycle 0 is generated
	asynchronous waitstate insertion
	pin #WAIT is low active
	read cycle multiplier is 1
	read access waitstates: 1
	cycle multiplier is 1
	write access waitstates: 2
	hold/pause cycle waitstates: 0
	recovery cycles waitstates: 0

	this register must be set in the start-up file
	EBU_EMUAS  =  0xBE000031;
	EBU_EMUBC  =  0x00160280;

	End of Important Settings for the Start-Up File

	Clock System:
	- external clock frequency: 16,000 MHz
	- PLL operation (pin BYPASS = 0)
	- clock factor (N-factor): 10 (pins CLKSEL[2:0] = 0x2)
	- VCO output frequency: 160,000 MHz
	- clock divider (K-factor): 4
	- system clock: 40,000 MHz

	Interrupt System:
	- four arbitration cycles (max. 255 interrupt sources)
	- two clocks per arbitration cycle

	Peripheral Control Processor (PCP):
	- four arbitration cycles (max. 255 PCP channels)
	- two clocks per arbitration cycle
	- use Full Context save area (R[0] - R[7])
	- channel start at context PC
	- the PCP error interrupt is disabled
	- PRAM partitioning is disabled
	- channel watchdog is disabled

	System Start Conditions:

	- the CPU interrupt system is globally enabled

	- the PCP interrupt system is globally disabled

General Purpose Timer Unit (GPTU)

Macros:
Functions:

	Function:
		void GPTU_vInit(void)
	Description:
		This is the initialization function of the GPTU function
		library. It is assumed that the SFRs used by this library
		are in its reset state.
	Returnvalue:
		None
	Parameters:
		None

	Function:
		void GPTU_viSRN0(void)
	Description:
		This is the interrupt service routine for the Service
		Request Node 0 of the GPTU module.
		Please note that you have to add application specific code
		to this function.
	Returnvalue:
		None
	Parameters:
		None

Initialization:

	Configuration of the Module Clock:
	- enable the GPTU module
	- clock divider for normal operation mode: System clock / 100 (=
	0,4000 MHz; 2500,000 ns )
	- the GPTU module is stopped during sleep mode

	Configuration of T0 and T1 Global Inputs:
	- T0 and T1 global input 0 selection: T2A over-/underflow
	- T0 and T1 global input 1 selection: T2B over-/underflow

	Configuration of T0 and T1:
	Timer T0A configuration:
	- timer T0A input selection: Clock input (= 0,400 MHz)
	- timer T0A overflows after 640,0000 µs
	- reload Timer T0A on overflow of timer T0A
	- timer T0A is stopped

	Timer T1A configuration:
	- timer T1A input selection: Clock input (= 0,400 MHz)
	- timer T1A overflows after 640,0000 µs
	- reload Timer T1A on overflow of timer T1A
	- timer T1A is stopped

	Timer T0B configuration:
	- timer T0B input selection: Clock input (= 0,400 MHz)
	- timer T0B overflows after 640,0000 µs
	- reload Timer T0B on overflow of timer T0B
	- timer T0B is stopped

	Timer T1B configuration:
	- timer T1B input selection: Clock input (= 0,400 MHz)
	- timer T1B overflows after 640,0000 µs
	- reload Timer T1B on overflow of timer T1B
	- timer T1B is stopped

	Timer T0C configuration:
	- timer T0C input selection: Clock input (= 0,400 MHz)
	- timer T0C overflows after 640,0000 µs
	- reload Timer T0C on overflow of timer T0C
	- timer T0C is stopped

	Timer T1C configuration:
	- timer T1C input selection: Clock input (= 0,400 MHz)
	- timer T1C overflows after 640,0000 µs
	- reload Timer T1C on overflow of timer T1C
	- timer T1C is stopped

	Timer T0D configuration:
	- timer T0D input selection: Clock input (= 0,400 MHz)
	- timer T0D overflows after 640,0000 µs
	- reload Timer T0D on overflow of timer T0D
	- timer T0D is stopped

	Timer T1D configuration:
	- timer T1D input selection: Clock input (= 0,400 MHz)
	- timer T1D overflows after 640,0000 µs
	- reload Timer T1D on overflow of timer T1D
	- timer T1D is stopped

	Configuration of T0 and T1 Output Signals:
	- output source selection OUT00: T0A overflow
	- output source selection OUT01: T0A overflow
	- output source selection OUT10: T1A overflow
	- output source selection OUT11: T1A overflow
	- trigger output source selection TRG00: T0A overflow
	- trigger output source selection TRG01: T0A overflow
	- trigger output source selection TRG10: T1A overflow
	- trigger output source selection TRG11: T1A overflow
	- service request source selection SR00: T0A overflow
	- service request source selection SR01: T0A overflow
	- service request source selection SR10: T1A overflow
	- service request source selection SR11: T1A overflow

	Timer T2 Split Mode:
	- timer T2 operates as two independent 16-bit timers T2A and T2B

	Configuration of T2A External Inputs:
	- external start input selection: input is disabled
	- external stop input selection: input is disabled
	- external up/down input selection: input is disabled
	- external clear input selection: input is disabled
	- external reload/capture 0 input selection: T0A overflow
	- external reload/capture 1 input selection: T0A overflow
	- external count input selection: T1A overflow

	Configuration of T2B External Inputs:
	- external start input selection: input is disabled
	- external stop input selection: input is disabled
	- external up/down input selection: input is disabled
	- external clear input selection: input is disabled
	- external reload/capture 0 input selection: T0A overflow
	- external reload/capture 1 input selection: T0A overflow
	- external count input selection: T0A overflow

	Configuration of T2A:
	- timer T2A input clock (= 0,400 MHz)
	- clear on external signal Clear_A (= input is disabled)
	- T2A continues to run after over- or underflow
	- T2A count up (software controlled)
	- timer T2A is started
	- T2A overflow is generated for FF..FF -> 00..00, underflow for 00..00
	-> FF..FF

	T2A capture/reload 0 configuration:
	- reload on overflow only
	T2A capture/reload 1 configuration:
	- T2A capture/reload mode is disabled

	Configuration of T2B:
	- timer T2B input clock (= 0,400 MHz)
	- clear on external signal Clear_B (= input is disabled)
	- T2B continues to run after over- or underflow
	- T2B count up (software controlled)
	- timer T2B is stopped
	- T2B overflow is generated for FF..FF -> 00..00, underflow for 00..00
	-> FF..FF

	T2B capture/reload 0 configuration:
	- T2B capture/reload mode is disabled
	T2B capture/reload 1 configuration:
	- T2B capture/reload mode is disabled

	Configuration of GPTU External Outputs:
	- output 0 source selection: Timer T2 signal OUV_T2A (over/underflow
	on T2A)
	- output 1 source selection: Timer T0 signal OUT00 (= T0A overflow)
	- output 2 source selection: Timer T0 signal OUT00 (= T0A overflow)
	- output 3 source selection: Timer T0 signal OUT00 (= T0A overflow)
	- output 4 source selection: Timer T0 signal OUT00 (= T0A overflow)
	- output 5 source selection: Timer T0 signal OUT00 (= T0A overflow)
	- output 6 source selection: Timer T0 signal OUT00 (= T0A overflow)
	- output 7 source selection: Timer T0 signal OUT00 (= T0A overflow)

	Configuration of the used GPTU Port Pins:

	Configuration of Service Request Nodes 0 - 7:

	GPTU service request node 0 configuration:
	- source selection: Timer T2A signal OUV_T2A
	- SRN0 service request node configuration:
	- SRN0 interrupt priority level (SRPN) = 5
	- SRN0 CPU interrupt is selected

	GPTU service request node 1 configuration:
	- source selection: Timer T2A signal Start_A (= input is disabled)

	GPTU service request node 2 configuration:
	- source selection: Timer T2A signal Start_A (= input is disabled)

	GPTU service request node 3 configuration:
	- source selection: Timer T2A signal Start_A (= input is disabled)

	GPTU service request node 4 configuration:
	- source selection: Timer T2A signal Start_A (= input is disabled)

	GPTU service request node 5 configuration:
	- source selection: Timer T2A signal Start_A (= input is disabled)

	GPTU service request node 6 configuration:
	- source selection: Timer T2A signal Start_A (= input is disabled)

	GPTU service request node 7 configuration:
	- source selection: Timer T2A signal Start_A (= input is disabled)

Real Time Clock (RTC)

Macros:
Functions:

	Function:
		void RTC_vInit(void)
	Description:
		This is the initialization function of the RTC function
		library. It is assumed that the SFRs used by this library
		are in its reset state.
	Returnvalue:
		None
	Parameters:
		None

	Function:
		void RTC_vRTCRun(void)
	Description:
		This function starts the RTC timer.
	Returnvalue:
		None
	Parameters:
		None

	Function:
		uword RTC_uwGetTime(void)
	Description:
		This function returns the contents of the RTC timer (CNT).
	Returnvalue:
		Value of the timer
	Parameters:
		None

	Function:
		void RTC_vReset(void)
	Description:
		This function loads the RTC timer (CNT) and the reload
		register (REL) with the value 0x00000000.
	Returnvalue:
		None
	Parameters:
		None

Initialization:

	Configuration of the Module Clock:
	- enable the RTC module
	- the RTC module is stopped during sleep mode

	Configuration of the RTC Counter:
	- RTC OSC frequency is 32,768 kHz
	- the input clock is divided by factor 8

	- overflow period on T14:  1,0000 [s]
	- overflow period on CNT0: 1,0000 [min]
	- overflow period on CNT1: 1,0000 [h]
	- overflow period on CNT2: 1,0000 [days]
	- overflow period on CNT3: 1,0000 [years]

	Configuration of the used RTC Interrupts: