; TASKING TriCore C compiler v1.5r1 Build 322 SN 00090364
; options: -e -A1 -g -O0 -Id:\ctri\include -s -N8 -zTC112_COR1 -zTC112_COR4
;          -zTC112_COR10 -zTC112_COR13 -zTC112_COR14 -zTC112_COR16 -zTC112_COR17
	.name	"main"
	.symb	TOOL, "TASKING TriCore C compiler v1.5", 1
	.symb	TYPE, 256, "bit", 'g', 0, 1
	.symb	FILE, "main.c"
; file "main.c":
;    1 |//****************************************************************************
;    2 |// @Module        Project Settings
;    3 |// @Filename      MAIN.C
;    4 |// @Project       BurstFlash.dav
;    5 |//----------------------------------------------------------------------------
;    6 |// @Controller    Infineon TC1775 B-Step
;    7 |//
;    8 |// @Compiler      Tasking
;    9 |//
;   10 |// @Codegenerator 2.2
;   11 |//
;   12 |// @Description   This file contains the project initialization function.
;   13 |//
;   14 |//----------------------------------------------------------------------------
;   15 |// @Date          17.07.2002 12:07:25
;   16 |//
;   17 |//****************************************************************************
;   18 |
;   19 |// USER CODE BEGIN (MAIN_General,1)
;   20 |
;   21 |// USER CODE END
;   22 |
;   23 |
;   24 |
;   25 |//****************************************************************************
;   26 |// @Project Includes
;   27 |//****************************************************************************
;   28 |
;   29 |#include "MAIN.H"
	.symb	FILE, "MAIN.H"
	.symb	TYPE, 257, "uword", 'T', #18
	.symb	FILE, "TC1775BRegs.h"
	.symb	ENDF
	.symb	FILE, "ASC0.H"
	.symb	TYPE, 258, "ushort", 'T', #5
	.symb	ENDF
	.symb	ENDF
;   30 |
;   31 |// USER CODE BEGIN (MAIN_General,2)
;   32 |#include "stdio.h"
	.symb	FILE, "d:\\ctri\\include\\stdio.h"
	.symb	FILE, "d:\\ctri\\include\\stdarg.h"
	.symb	ENDF
	.symb	TYPE, 260, 'P', #2
	.symb	TYPE, 261, "_iobuf", 'S', 24,\
		 "_ptr", #260, 0,\
		 "_base", #260, 4,\
		 "_cnt", #16, 8,\
		 "_bufsiz", #16, 12,\
		 "_flag", #5, 16,\
		 "_file", #2, 18,\
		 "_wcnt", #16, 20
	.symb	TYPE, 262, "FILE", 'T', #261
	.symb	TYPE, 263, "va_list", 'T', #260
	.symb	TYPE, 264, "size_t", 'T', #18
	.symb	TYPE, 265, "fpos_t", 'T', #7
	.symb	TYPE, 266, "off_t", 'T', #6
	.symb	ENDF
;   33 |#include "stdlib.h"
	.symb	FILE, "d:\\ctri\\include\\stdlib.h"
	.symb	TYPE, 267, 'S', 8,\
		 "quot", #16, 0,\
		 "rem", #16, 4
	.symb	TYPE, 268, "div_t", 'T', #267
	.symb	TYPE, 269, 'S', 8,\
		 "quot", #6, 0,\
		 "rem", #6, 4
	.symb	TYPE, 270, "ldiv_t", 'T', #269
	.symb	TYPE, 271, "wchar_t", 'T', #16
	.symb	ENDF
;   34 |#include "ifu.h"
	.symb	FILE, "ifu.h"
	.symb	ENDF
;   35 |// USER CODE END
;   36 |
;   37 |
;   38 |//****************************************************************************
;   39 |// @Macros
;   40 |//****************************************************************************
;   41 |
;   42 |// USER CODE BEGIN (MAIN_General,3)
;   43 |
;   44 |// USER CODE END
;   45 |
;   46 |
;   47 |//****************************************************************************
;   48 |// @Defines
;   49 |//****************************************************************************
;   50 |
;   51 |#define RESET_INDICATOR     ((RST_SR & 0xFF000000) >> 24)
;   52 |#define DEEPSLEEP_WAKEUP    0x80
;   53 |#define WATCHDOG_RESET      0x40
;   54 |#define SOFTWARE_RESET      0x20
;   55 |#define HARDWARE_RESET      0x10
;   56 |#define POWERON_RESET       0x08
;   57 |
;   58 |// USER CODE BEGIN (MAIN_General,4)
;   59 |
;   60 |// USER CODE END
;   61 |
;   62 |
;   63 |//****************************************************************************
;   64 |// @Typedefs
;   65 |//****************************************************************************
;   66 |
;   67 |// USER CODE BEGIN (MAIN_General,5)
;   68 |
;   69 |// USER CODE END
;   70 |
;   71 |
;   72 |//****************************************************************************
;   73 |// @Imported Global Variables
;   74 |//****************************************************************************
;   75 |
;   76 |// USER CODE BEGIN (MAIN_General,6)
;   77 |
;   78 |// USER CODE END
;   79 |
;   80 |
;   81 |//****************************************************************************
;   82 |// @Global Variables
;   83 |//****************************************************************************
;   84 |
;   85 |// USER CODE BEGIN (MAIN_General,7)
;   86 |//unsigned int i,count,null;
;   87 |char 		 buffer[80];
;   88 |unsigned char count;
;   89 |//unsigned char	count;
;   90 |// USER CODE END
;   91 |
;   92 |
;   93 |//****************************************************************************
;   94 |// @External Prototypes
;   95 |//****************************************************************************
;   96 |
;   97 |// USER CODE BEGIN (MAIN_General,8)
;   98 |void sieve (void);
;   99 |// USER CODE END
;  100 |
;  101 |
;  102 |//****************************************************************************
;  103 |// @Prototypes Of Local Functions
;  104 |//****************************************************************************
;  105 |
;  106 |// USER CODE BEGIN (MAIN_General,9)
;  107 |
;  108 |// USER CODE END
;  109 |
;  110 |
;  111 |//****************************************************************************
;  112 |// @Function      void MAIN_vInit(void) 
;  113 |//
;  114 |//----------------------------------------------------------------------------
;  115 |// @Description   This function initializes the microcontroller.
;  116 |//
;  117 |//----------------------------------------------------------------------------
;  118 |// @Returnvalue   None
;  119 |//
;  120 |//----------------------------------------------------------------------------
;  121 |// @Parameters    None
;  122 |//
;  123 |//----------------------------------------------------------------------------
;  124 |// @Date          17.07.2002
;  125 |//
;  126 |//****************************************************************************
;  127 |
;  128 |// USER CODE BEGIN (Init,1)
;  129 |
;  130 |// USER CODE END
;  131 |
;  132 |void MAIN_vInit(void)
;  133 |{
	.sdecl	"code.main",CODE
	.sect	"code.main"
	.align	4
	.symb	LINE, 133
	.symb	TYPE, 272, 'X', 8, #1, 26, 0
	.symb	GFUN, "MAIN_vInit", MAIN_vInit, #272, 0, 0, 0
	.symb	ALAB, MAIN_vInit, #272
MAIN_vInit:
	.symb	SOFF, 0
;  134 |  // USER CODE BEGIN (Init,2)
;  135 |
;  136 |  // USER CODE END
;  137 |
;  138 |  //// -----------------------------------------------------------------------
;  139 |  //// Begin of Important Settings for the Start-Up File
;  140 |  //// -----------------------------------------------------------------------
;  141 |  ///  All following settings must be set in the start-up file. You can use 
;  142 |  ///  DAvE's project file (*.dpt) to include this register values into your 
;  143 |  ///  compiler EDE.
;  144 |
;  145 |    ///  ---------------------------------------------------------------------
;  146 |    ///  Bus Control Unit (BCU):
;  147 |    ///  ---------------------------------------------------------------------
;  148 |    ///  BCU starvation protection is enabled
;  149 |    ///  BCU power saving is disabled
;  150 |    ///  the debug trace is enabled. Error information is captured in 
;  151 |    ///  register BCEADD, BCEDAT and BCECON
;  152 |    ///  sample period of request for starvation protection: 64
;  153 |    ///  BCU bus time-out value: 65536 cycles
;  154 |
;  155 |    //// this register must be set in the start-up file
;  156 |    //// BCU_CON  =  0x4009FFFF;
;  157 |
;  158 |    ///  ---------------------------------------------------------------------
;  159 |    ///  Program Memory Unit (PMU):
;  160 |    ///  ---------------------------------------------------------------------
;  161 |    ///  ICACHE settings:
;  162 |    ///  the instruction cache is enabled
;  163 |    ///  RFB refill operation is terminated on a cache miss which occurs on 
;  164 |    ///  an access to an external burst mode code memory
;  165 |
;  166 |    //// this register must be set in the start-up file
;  167 |    //// PMU_CON  =  0x04000714;
;  168 |
;  169 |    ///  external flash settings:
;  170 |    ///  min. wait cycles between consecutive burst accesses from external 
;  171 |    ///  Flash: 0 wait cycles
;  172 |    ///  read wait cycles between the initial address and the first data 
;  173 |    ///  cycle: 0 wait cycles
;  174 |    ///  two address cycles
;  175 |    ///  one data cycle
;  176 |    ///  max. number of linear Flash burst data cycles: 32 burst data cycles
;  177 |    ///  max. number of burst data cycle: 1 data accesses
;  178 |    ///  #WAIT input operates as a terminate burst function
;  179 |    ///  #CS0 is activated during burst mode
;  180 |
;  181 |    //// this register must be set in the start-up file
;  182 |    //// PMU_EIFCON  =  0x00000261;
;  183 |
;  184 |    ///  ---------------------------------------------------------------------
;  185 |    ///  External Bus Unit (EBU):
;  186 |    ///  ---------------------------------------------------------------------
;  187 |
;  188 |    ///  enable the EBU module
;  189 |
;  190 |    //// this register must be set in the start-up file
;  191 |    //// EBU_CLC  =  0x00000000;
;  192 |
;  193 |    ///  External Arbitration:
;  194 |    ///  EBU is external master
;  195 |    ///  arbitration inputs are asynchronous
;  196 |    ///  external bus will not be locked after EBU gained ownership
;  197 |    ///  enable external accesses to FPI bus
;  198 |    ///  disable external address extension register reconfiguration
;  199 |    ///  all accesses from external master are performed in user mode
;  200 |    ///  disable Time-out
;  201 |    ///  chip select triggered driver turn-around inactive cycles: 0
;  202 |    ///  read-write triggered driver turn-around inactive cycles: 0
;  203 |
;  204 |    //// this register must be set in the start-up file
;  205 |    //// EBU_CON  =  0x00000068;
;  206 |
;  207 |    ///  Overlay Memory:
;  208 |    ///  do not activate chip select #CSOVL on an access to memory region 0
;  209 |    ///  do not activate chip select #CSOVL on an access to memory region 1
;  210 |    ///  do not activate chip select #CSOVL on an access to memory region 2
;  211 |    ///  do not activate chip select #CSOVL on an access to memory region 3
;  212 |
;  213 |    //// this register must be set in the start-up file
;  214 |    //// EBU_EMUCON  =  0x00000000;
;  215 |
;  216 |    ///  Address Region 0:
;  217 |    ///  enable memory region 0
;  218 |    ///  length of the region: 128 Mbyte
;  219 |    ///  relevant start address (A31 : A0): 0xA0000000
;  220 |    ///  writes to memory region are disabled
;  221 |    ///  address generation: demuxed address mode
;  222 |    ///  external device data width: 32-bit
;  223 |    ///  address latch enable (ALE) duration: 3 cycles
;  224 |    ///  byte control signal timing mode: control mode
;  225 |    ///  cycle 0 is not generated
;  226 |    ///  variable waitstate insertion is disabled
;  227 |    ///  pin #WAIT is low active
;  228 |    ///  read cycle multiplier is 1
;  229 |    ///  read access waitstates: 48
;  230 |    ///  cycle multiplier is 16
;  231 |    ///  write access waitstates: 112
;  232 |    ///  hold/pause cycle waitstates: 48
;  233 |    ///  recovery cycles waitstates: 48
;  234 |
;  235 |    //// this register must be set in the start-up file
;  236 |    //// EBU_ADDSEL0  =  0xA0000001;
;  237 |    //// EBU_BUSCON0  =  0xE80261FF;
;  238 |
;  239 |    ///  Address Region 1:
;  240 |    ///  enable memory region 1
;  241 |    ///  length of the region: 128 Mbyte
;  242 |    ///  relevant start address (A31 : A0): 0xA0000000
;  243 |    ///  writes to memory region are disabled
;  244 |    ///  address generation: demuxed address mode
;  245 |    ///  external device data width: 32-bit
;  246 |    ///  address latch enable (ALE) duration: 3 cycles
;  247 |    ///  byte control signal timing mode: control mode
;  248 |    ///  cycle 0 is not generated
;  249 |    ///  variable waitstate insertion is disabled
;  250 |    ///  pin #WAIT is low active
;  251 |    ///  read cycle multiplier is 1
;  252 |    ///  read access waitstates: 48
;  253 |    ///  cycle multiplier is 16
;  254 |    ///  write access waitstates: 112
;  255 |    ///  hold/pause cycle waitstates: 48
;  256 |    ///  recovery cycles waitstates: 48
;  257 |
;  258 |    //// this register must be set in the start-up file
;  259 |    //// EBU_ADDSEL1  =  0xA0000001;
;  260 |    //// EBU_BUSCON1  =  0xE80261FF;
;  261 |
;  262 |    ///  Address Region 2:
;  263 |    ///  enable memory region 2
;  264 |    ///  length of the region: 128 Mbyte
;  265 |    ///  relevant start address (A31 : A0): 0xA0000000
;  266 |    ///  writes to memory region are disabled
;  267 |    ///  address generation: demuxed address mode
;  268 |    ///  external device data width: 32-bit
;  269 |    ///  address latch enable (ALE) duration: 3 cycles
;  270 |    ///  byte control signal timing mode: control mode
;  271 |    ///  cycle 0 is not generated
;  272 |    ///  variable waitstate insertion is disabled
;  273 |    ///  pin #WAIT is low active
;  274 |    ///  read cycle multiplier is 1
;  275 |    ///  read access waitstates: 48
;  276 |    ///  cycle multiplier is 16
;  277 |    ///  write access waitstates: 112
;  278 |    ///  hold/pause cycle waitstates: 48
;  279 |    ///  recovery cycles waitstates: 48
;  280 |
;  281 |    //// this register must be set in the start-up file
;  282 |    //// EBU_ADDSEL2  =  0xA0000001;
;  283 |    //// EBU_BUSCON2  =  0xE80261FF;
;  284 |
;  285 |    ///  Address Region 3:
;  286 |    ///  enable memory region 3
;  287 |    ///  length of the region: 128 Mbyte
;  288 |    ///  relevant start address (A31 : A0): 0xA0000000
;  289 |    ///  writes to memory region are disabled
;  290 |    ///  address generation: demuxed address mode
;  291 |    ///  external device data width: 32-bit
;  292 |    ///  address latch enable (ALE) duration: 3 cycles
;  293 |    ///  byte control signal timing mode: control mode
;  294 |    ///  cycle 0 is not generated
;  295 |    ///  variable waitstate insertion is disabled
;  296 |    ///  pin #WAIT is low active
;  297 |    ///  read cycle multiplier is 1
;  298 |    ///  read access waitstates: 48
;  299 |    ///  cycle multiplier is 16
;  300 |    ///  write access waitstates: 112
;  301 |    ///  hold/pause cycle waitstates: 48
;  302 |    ///  recovery cycles waitstates: 48
;  303 |
;  304 |    //// this register must be set in the start-up file
;  305 |    //// EBU_ADDSEL3  =  0xA0000001;
;  306 |    //// EBU_BUSCON3  =  0xE80261FF;
;  307 |
;  308 |    ///  Emulator Address Region :
;  309 |    ///  enable emulator memory region
;  310 |    ///  length of the region: 16 Mbyte
;  311 |    ///  relevant start address (A31 : A0): 0xBE000000
;  312 |    ///  writes to memory region are enabled
;  313 |    ///  address generation: demuxed address mode
;  314 |    ///  external device data width: 32-bit
;  315 |    ///  address latch enable (ALE) duration: 0 cycles
;  316 |    ///  byte control signal timing mode: chipselect mode
;  317 |    ///  cycle 0 is generated
;  318 |    ///  asynchronous waitstate insertion
;  319 |    ///  pin #WAIT is low active
;  320 |    ///  read cycle multiplier is 1
;  321 |    ///  read access waitstates: 1
;  322 |    ///  cycle multiplier is 1
;  323 |    ///  write access waitstates: 2
;  324 |    ///  hold/pause cycle waitstates: 0
;  325 |    ///  recovery cycles waitstates: 0
;  326 |
;  327 |    //// this register must be set in the start-up file
;  328 |    //// EBU_EMUAS  =  0xBE000031;
;  329 |    //// EBU_EMUBC  =  0x00160280;
;  330 |
;  331 |  //// -----------------------------------------------------------------------
;  332 |  //// End of Important Settings for the Start-Up File
;  333 |  //// -----------------------------------------------------------------------
;  334 |
;  335 |  ///  -----------------------------------------------------------------------
;  336 |  ///  Clock System:
;  337 |  ///  -----------------------------------------------------------------------
;  338 |  ///  - external clock frequency: 16,000 MHz
;  339 |  ///  - PLL operation (pin BYPASS = 0)
;  340 |  ///  - clock factor (N-factor): 10 (pins CLKSEL[2:0] = 0x2)
;  341 |  ///  - VCO output frequency: 160,000 MHz
;  342 |  ///  - clock divider (K-factor): 4
;  343 |  ///  - system clock: 40,000 MHz
;  344 |
;  345 |  MAIN_vResetENDINIT();
	.symb	LINE, 345
	ld.w	d4,-268435424
	mov16	d15,#-2				; -2
	and16	d4,d15
	callg	MAIN_vWriteWDTCON0
;  346 |  PLL_CLC        =  0x00020000;  // load PLL clock control register
	.symb	LINE, 346
	movh	d15,#0x2
	st.w	-268435392,d15
;  347 |  MAIN_vSetENDINIT();
	.symb	LINE, 347
	ld.w	d4,-268435424
	or	d4,d4,#1
	callg	MAIN_vWriteWDTCON0
;  348 |
;  349 |  ///  -----------------------------------------------------------------------
;  350 |  ///  Interrupt System:
;  351 |  ///  -----------------------------------------------------------------------
;  352 |  ///  - four arbitration cycles (max. 255 interrupt sources)
;  353 |  ///  - two clocks per arbitration cycle
;  354 |
;  355 |  MTCR(0xFE2C,  0x00000000);     // load CPU interrupt control register
	.symb	LINE, 355
	mov16	d15,#0				; 0
	mtcr	#65068,d15			; 65068
;  356 |  ISYNC();
	.symb	LINE, 356
	isync
;  357 |
;  358 |  ///  -----------------------------------------------------------------------
;  359 |  ///  Peripheral Control Processor (PCP):
;  360 |  ///  -----------------------------------------------------------------------
;  361 |  ///  - four arbitration cycles (max. 255 PCP channels)
;  362 |  ///  - two clocks per arbitration cycle
;  363 |  ///  - use Full Context save area (R[0] - R[7])
;  364 |  ///  - channel start at context PC
;  365 |  ///  - the PCP error interrupt is disabled
;  366 |  ///  - PRAM partitioning is disabled
;  367 |  ///  - channel watchdog is disabled
;  368 |
;  369 |  MAIN_vResetENDINIT();
	.symb	LINE, 369
	ld.w	d4,-268435424
	mov16	d15,#-2				; -2
	and16	d4,d15
	callg	MAIN_vWriteWDTCON0
;  370 |  PCP_CS         =  0x00020800;  // load PCP control and status register
	.symb	LINE, 370
	mov.u	d15,#0x800
	addih	d15,d15,#0x2
	st.w	-268419312,d15
;  371 |  MAIN_vSetENDINIT();
	.symb	LINE, 371
	ld.w	d4,-268435424
	or	d4,d4,#1
	callg	MAIN_vWriteWDTCON0
;  372 |
;  373 |  PCP_ICR        =  0x00000000;  // load PCP interrupt control register
	.symb	LINE, 373
	mov16	d15,#0
	st.w	-268419296,d15
;  374 |
;  375 |  //   -----------------------------------------------------------------------
;  376 |  //   Initialization of the Peripherals:
;  377 |  //   -----------------------------------------------------------------------
;  378 |  //   initializes the Asynchronous Synchronous Serial Interface 0 (ASC0)
;  379 |  ASC0_vInit();
	.symb	LINE, 379
	callg	ASC0_vInit
;  380 |
;  381 |
;  382 |  // USER CODE BEGIN (Init,3)
;  383 |
;  384 |  // USER CODE END
;  385 |
;  386 |  ///  -----------------------------------------------------------------------
;  387 |  ///  System Start Conditions:
;  388 |  ///  -----------------------------------------------------------------------
;  389 |
;  390 |  //// - the CPU interrupt system is globally disabled
;  391 |  DISABLE();
	.symb	LINE, 391
	disable
;  392 |
;  393 |  //// - the PCP interrupt system is globally disabled
;  394 |
;  395 |
;  396 |  // USER CODE BEGIN (Init,4)
;  397 |
;  398 |  // USER CODE END
;  399 |
;  400 |} //  End of function MAIN_vInit
	.symb	LINE, 400
	ret16
	.symb	EFUN
;  401 |
;  402 |
;  403 |//****************************************************************************
;  404 |// @Function      void MAIN_vWriteWDTCON0(uword uwValue) 
;  405 |//
;  406 |//----------------------------------------------------------------------------
;  407 |// @Description   This function writes the parameter uwValue to the WDT_CON0 
;  408 |//                register which is password protected. 
;  409 |//
;  410 |//----------------------------------------------------------------------------
;  411 |// @Returnvalue   None
;  412 |//
;  413 |//----------------------------------------------------------------------------
;  414 |// @Parameters    uwValue: 
;  415 |//                Value for the WDTCON0 register
;  416 |//
;  417 |//----------------------------------------------------------------------------
;  418 |// @Date          17.07.2002
;  419 |//
;  420 |//****************************************************************************
;  421 |
;  422 |// USER CODE BEGIN (WriteWDTCON0,1)
;  423 |
;  424 |// USER CODE END
;  425 |
;  426 |void MAIN_vWriteWDTCON0(uword uwValue)
;  427 |{
	.symb	LINE, 427
	.symb	TYPE, 273, 'g', 0, 1
	.symb	TYPE, 274, 'g', 0, 1
	.symb	TYPE, 275, 'g', 0, 1
	.symb	TYPE, 276, 'g', 0, 1
	.symb	TYPE, 277, 'g', 0, 1
	.symb	TYPE, 278, 'g', 0, 1
	.symb	TYPE, 279, 'g', 0, 1
	.symb	TYPE, 280, 'g', 0, 1
	.symb	TYPE, 281, 'g', 0, 1
	.symb	TYPE, 282, 'g', 0, 1
	.symb	TYPE, 283, 'g', 0, 1
	.symb	TYPE, 284, 'g', 0, 1
	.symb	TYPE, 285, 'g', 0, 1
	.symb	TYPE, 286, 'g', 0, 1
	.symb	TYPE, 287, 'g', 0, 1
	.symb	TYPE, 288, 'g', 0, 1
	.symb	TYPE, 289, 'g', 0, 1
	.symb	TYPE, 290, 'g', 0, 1
	.symb	TYPE, 291, 'g', 0, 1
	.symb	TYPE, 292, 'g', 0, 1
	.symb	TYPE, 293, 'g', 0, 1
	.symb	TYPE, 294, 'g', 0, 1
	.symb	TYPE, 295, 'g', 0, 1
	.symb	TYPE, 296, 'g', 0, 1
	.symb	TYPE, 297, 'g', 0, 1
	.symb	TYPE, 298, 'g', 0, 1
	.symb	TYPE, 299, 'g', 0, 1
	.symb	TYPE, 300, 'g', 0, 1
	.symb	TYPE, 301, 'g', 0, 1
	.symb	TYPE, 302, 'g', 0, 1
	.symb	TYPE, 303, 'g', 0, 1
	.symb	TYPE, 304, 'g', 0, 1
	.symb	TYPE, 305, 'S', 4,\
		 "bit0", #273, 0,\
		 "bit1", #274, 1,\
		 "bit2", #275, 2,\
		 "bit3", #276, 3,\
		 "bit4", #277, 4,\
		 "bit5", #278, 5,\
		 "bit6", #279, 6,\
		 "bit7", #280, 7,\
		 "bit8", #281, 8,\
		 "bit9", #282, 9,\
		 "bit10", #283, 10,\
		 "bit11", #284, 11,\
		 "bit12", #285, 12,\
		 "bit13", #286, 13,\
		 "bit14", #287, 14,\
		 "bit15", #288, 15,\
		 "bit16", #289, 16,\
		 "bit17", #290, 17,\
		 "bit18", #291, 18,\
		 "bit19", #292, 19,\
		 "bit20", #293, 20,\
		 "bit21", #294, 21,\
		 "bit22", #295, 22,\
		 "bit23", #296, 23,\
		 "bit24", #297, 24,\
		 "bit25", #298, 25,\
		 "bit26", #299, 26,\
		 "bit27", #300, 27,\
		 "bit28", #301, 28,\
		 "bit29", #302, 29,\
		 "bit30", #303, 30,\
		 "bit31", #304, 31
	.symb	TYPE, 306, "T_Reg32", 'T', #305
	.symb	TYPE, 307, 'X', 8, #1, 26, 1, #18
	.symb	GFUN, "MAIN_vWriteWDTCON0", MAIN_vWriteWDTCON0, #307, 0, 16, 0
	.symb	ALAB, MAIN_vWriteWDTCON0, #307
MAIN_vWriteWDTCON0:
	.symb	SOFF, 16
	.symb	LTIM, "uwValue", 4, 0, 0x8cd
	.symb	IDEN, "uwValue", 4, #18, 0, 0x80d
	.symb	IDEN, "uwDummy", -12, #18, 131, 0x5
	.symb	LTIM, "uwValue", 4, 0, 0x84d
	.symb	LTIM, "uwValue", -16, 131, 0x8c5
	nop
	sub16.a	sp,#16
;  428 |  uword uwDummy;
	.symb	LINE, 428
	st16.w	[sp],d4				; uwValue
;  429 |
;  430 |  uwDummy  =  WDT_CON0;
	.symb	LINE, 430
	ld.w	d15,-268435424
	st16.w	[sp]4,d15			; uwDummy
;  431 |  uwDummy |=  0x000000F0;       //  set HWPW1 = 1111b
	.symb	LINE, 431
	ld16.w	d15,[sp]4			; uwDummy
	or	d15,d15,#240			; uwDummy
	st16.w	[sp]4,d15			; uwDummy
;  432 |
;  433 |  if(WDT_CON1_WDTDR)
	.symb	LINE, 433
	ld.bu	d15,-268435420
	extr.u	d15,d15,#3,#1
	jeq	d15,#0,_17
;  434 |  {
;  435 |    uwDummy |=  0x00000008;     //  set HWPW0 = WDTDR
	.symb	LINE, 435
	ld16.w	d15,[sp]4			; uwDummy
	or	d15,d15,#8			; uwDummy
	st16.w	[sp]4,d15			; uwDummy
;  436 |  }
	.symb	LINE, 436
	j	_18
_17:
;  437 |  else
;  438 |  {
;  439 |    uwDummy &= ~0x00000008;     //  set HWPW0 = WDTDR
	.symb	LINE, 439
	nop
	ld16.w	d15,[sp]4			; uwDummy
	mov	d7,#-9				; -9
	and16	d15,d7				; uwDummy
	st16.w	[sp]4,d15			; uwDummy
;  440 |  }
	.symb	LINE, 440
_18:
;  441 |  if(WDT_CON1_WDTIR)
	.symb	LINE, 441
	ld.bu	d15,-268435420
	extr.u	d15,d15,#2,#1
	jeq	d15,#0,_19
;  442 |  {
;  443 |    uwDummy |=  0x00000004;     //  set HWPW0 = WDTIR
	.symb	LINE, 443
	ld16.w	d15,[sp]4			; uwDummy
	or	d15,d15,#4			; uwDummy
	st16.w	[sp]4,d15			; uwDummy
;  444 |  }
	.symb	LINE, 444
	j	_20
_19:
;  445 |  else
;  446 |  {
;  447 |    uwDummy &= ~0x00000004;     //  set HWPW0 = WDTIR
	.symb	LINE, 447
	nop
	ld16.w	d15,[sp]4			; uwDummy
	mov16	d7,#-5				; -5
	and16	d15,d7				; uwDummy
	st16.w	[sp]4,d15			; uwDummy
;  448 |  }
	.symb	LINE, 448
_20:
	.symb	LTIM, "uwValue", -16, 131, 0x845
	.symb	LTIM, "uwValue", 15, 0, 0x8cd
	.symb	LTIM, "uwValue", 15, 0, 0x84d
	.symb	LTIM, "uwValue", 15, 0, 0x8cd
	.symb	LTIM, "uwValue", 15, 0, 0x84d
	.symb	LTIM, "uwValue", -16, 131, 0x8c5
	.symb	LTIM, "uwValue", -16, 131, 0x845
	.symb	LTIM, "uwValue", 15, 0, 0x8cd
	.symb	LTIM, "uwValue", 15, 0, 0x84d
	.symb	LTIM, "uwValue", 15, 0, 0x8cd
	.symb	LTIM, "uwValue", 15, 0, 0x84d
	.symb	LTIM, "uwValue", -16, 131, 0x8c5
	.symb	LTIM, "uwValue", -16, 131, 0x845
	.symb	LTIM, "uwValue", 15, 0, 0x8cd
;  449 |
;  450 |  uwDummy &= ~0x00000002;       //  set WDTLCK = 0
	.symb	LINE, 450
	nop
	ld16.w	d15,[sp]4			; uwDummy
	mov16	d7,#-3				; -3
	and16	d15,d7				; uwDummy
	st16.w	[sp]4,d15			; uwDummy
;  451 |  WDT_CON0 =  uwDummy;          //  unlock access
	.symb	LINE, 451
	ld16.w	d15,[sp]4			; uwDummy
	st.w	-268435424,d15
;  452 |
;  453 |  uwValue  |=  0x000000F2;      //  set HWPW1 = 1111b and WDTLCK = 1
	.symb	LINE, 453
	ld16.w	d15,[sp]			; uwValue
	or	d15,d15,#242			; uwValue
	st16.w	[sp],d15			; uwValue
;  454 |  uwValue  &= ~0x0000000C;      //  set HWPW0 = 00b
	.symb	LINE, 454
	ld16.w	d15,[sp]			; uwValue
	mov	d7,#-13				; -13
	and16	d15,d7				; uwValue
	st16.w	[sp],d15			; uwValue
;  455 |  WDT_CON0  =  uwValue;         //  write access and lock
	.symb	LINE, 455
	ld16.w	d15,[sp]			; uwValue
	st.w	-268435424,d15
;  456 |
;  457 |} //  End of function MAIN_vWriteWDTCON0
	.symb	LINE, 457
	ret16
	.symb	LTIM, "uwValue", 15, 0, 0x84d
	.symb	EFUN
;  458 |
;  459 |
;  460 |//****************************************************************************
;  461 |// @Function      void main(void) 
;  462 |//
;  463 |//----------------------------------------------------------------------------
;  464 |// @Description   This is the main function.
;  465 |//
;  466 |//----------------------------------------------------------------------------
;  467 |// @Returnvalue   None
;  468 |//
;  469 |//----------------------------------------------------------------------------
;  470 |// @Parameters    None
;  471 |//
;  472 |//----------------------------------------------------------------------------
;  473 |// @Date          17.07.2002
;  474 |//
;  475 |//****************************************************************************
;  476 |
;  477 |// USER CODE BEGIN (Main,1)
;  478 |void TC1775_ASC0_printf(const char* fmt, ...)
;  479 |	{
	.symb	LINE, 479
	.symb	TYPE, 308, 'X', 8, #1, 26, 2, #260, #1
	.symb	GFUN, "TC1775_ASC0_printf", TC1775_ASC0_printf, #308, 0, 16, 0
	.symb	ALAB, TC1775_ASC0_printf, #308
TC1775_ASC0_printf:
	.symb	SOFF, 16
	.symb	LTIM, "fmt", 20, 0, 0x8cd
	.symb	IDEN, "fmt", 20, #260, 0, 0x80d
	.symb	IDEN, "ap", -12, #260, 131, 0x5
	.symb	IDEN, "ptr", -8, #260, 131, 0x5
	.symb	LTIM, "fmt", 20, 0, 0x84d
	.symb	LTIM, "fmt", -16, 131, 0x8c5
	.symb	LTIM, "fmt", -16, 131, 0x845
	.symb	LTIM, "fmt", 21, 0, 0x8cd
	.symb	LTIM, "fmt", 21, 0, 0x84d
	nop
	sub16.a	sp,#16
;  480 |	va_list ap;
;  481 |	char * ptr;
	.symb	LINE, 481
	st16.a	[sp],a4				; fmt
;  482 |
;  483 |	va_start(ap, fmt);
	.symb	LINE, 483
	lea	a15,[sp]16
	st16.a	[sp]4,a15			; ap
;  484 |	vsprintf(buffer, fmt, ap);
	.symb	LINE, 484
	movh.a	a4,#@his(buffer)
	lea	a4,[a4]@los(buffer)
	ld16.a	a5,[sp]				; fmt
	ld.a	a6,[sp]4			; ap
	callg	vsprintf
;  485 |	va_end(ap);
;  486 |
;  487 |	for(ptr = buffer;*ptr!='\0';ptr++)
	.symb	LINE, 487
	movh.a	a4,#@his(buffer)
	lea	a4,[a4]@los(buffer)
	st.a	[sp]8,a4			; ptr
	j	_26
_21:
;  488 |		{
;  489 |			while(! ASC0_ubTxBufFree());
	.symb	LINE, 489
	j	_24
_22:
_24:
_25:
	ld.bu	d15,-268433155
	extr.u	d15,d15,#5,#1
	jeq	d15,#0,_25
;  490 | 			ASC0_vSendData(*ptr);		
	.symb	LINE, 490
	ld16.a	a15,[sp]8			; ptr
	ld.b	d4,[a15]
	extr.u	d4,d4,#0,#16
	callg	ASC0_vSendData
	.symb	LINE, 487
	ld.a	a7,[sp]8			; ptr
	add16.a	a7,#1				; ptr
	st.a	[sp]8,a7			; ptr
_26:
	nop
	ld.a	a7,[sp]8			; ptr
	ld.b	d15,[a7]
	jne	d15,#0,_24
;  491 |		}
;  492 |	}
	.symb	LINE, 492
	ret16
	.symb	EFUN
;  493 |// USER CODE END
;  494 |
;  495 |void main(void)
;  496 |{
	.symb	LINE, 496
	.symb	TYPE, 309, 'X', 8, #1, 26, 0
	.symb	GFUN, "main", main, #309, 0, 0, 0
	.symb	ALAB, main, #309
main:
	.symb	SOFF, 0
;  497 |  // USER CODE BEGIN (Main,2)
;  498 |//unsigned int count;
;  499 |  // USER CODE END
;  500 |
;  501 |  switch(RESET_INDICATOR)
	.symb	LINE, 501
	ld.w	d15,-268435436
	movh	d7,#0xff00			; -16777216
	and16	d15,d7
	sh	d15,d15,#-24
	addi	d15,d15,#-16
	jeq	d15,#-8,_36			; case 8
	jeq	d15,#0,_35			; case 16
	addi	d15,d15,#-16
	jeq	d15,#0,_34			; case 32
	addi	d15,d15,#-32
	jeq	d15,#0,_33			; case 64
	addi	d15,d15,#-64
	jeq	d15,#0,_32			; case 128
	j	_37				; default
;  502 |  {
;  503 |    case DEEPSLEEP_WAKEUP:       //  the last reset was an external triggered
	.symb	LINE, 503
_32:
;  504 |                                 //  hardware reset in deep sleep mode 
;  505 |                                 //  (wake-up reset)
;  506 |
;  507 |         // USER CODE BEGIN (Main,3)
;  508 |
;  509 |         // USER CODE END
;  510 |
;  511 |    case WATCHDOG_RESET:         //  the last reset was a watchdog triggered
	.symb	LINE, 511
_33:
;  512 |                                 //  (hardware) reset
;  513 |
;  514 |         // USER CODE BEGIN (Main,4)
;  515 |
;  516 |         // USER CODE END
;  517 |
;  518 |    case SOFTWARE_RESET:         //  the last reset was an internally 
	.symb	LINE, 518
_34:
;  519 |                                 //  triggered software reset
;  520 |
;  521 |         // USER CODE BEGIN (Main,5)
;  522 |
;  523 |         // USER CODE END
;  524 |
;  525 |    case HARDWARE_RESET:         //  the last reset was an externally
	.symb	LINE, 525
_35:
;  526 |                                 //  triggered hardware reset (#HRST pin)
;  527 |
;  528 |         // USER CODE BEGIN (Main,6)
;  529 |
;  530 |         // USER CODE END
;  531 |
;  532 |    case POWERON_RESET:          //  the last reset was an externally
	.symb	LINE, 532
_36:
;  533 |                                 //  triggered power on reset (#POR pin)
;  534 |
;  535 |         // USER CODE BEGIN (Main,7)
;  536 |
;  537 |         // USER CODE END
;  538 |
;  539 |    default:
	.symb	LINE, 539
_37:
;  540 |
;  541 |         // USER CODE BEGIN (Main,8)
;  542 |
;  543 |         // USER CODE END
;  544 |
;  545 |         MAIN_vInit();
	.symb	LINE, 545
	callg	MAIN_vInit
;  546 |  }
	.symb	LINE, 546
_38:
;  547 |
;  548 |
;  549 |  // USER CODE BEGIN (Main,9)
;  550 |
;  551 |// Set prozessor speed to 40MHz
;  552 |MAIN_vResetENDINIT();
	.symb	LINE, 552
	ld.w	d4,-268435424
	mov16	d15,#-2				; -2
	and16	d4,d15
	callg	MAIN_vWriteWDTCON0
;  553 |PLL_CLC &=  ~(0x00050000);  // load PLL clock control register for 40MHz
	.symb	LINE, 553
	ld.w	d15,-268435392
	mov.u	d7,#0xffff			; -327681
	addih	d7,d7,#0xfffa			; -327681
	and16	d15,d7
	st.w	-268435392,d15
;  554 |MAIN_vSetENDINIT();
	.symb	LINE, 554
	ld.w	d4,-268435424
	or	d4,d4,#1
	callg	MAIN_vWriteWDTCON0
;  555 |
;  556 |
;  557 |TC1775_ASC0_printf("\n\rBurst Mode Demo Tricore TC1775\n\r");
	.symb	LINE, 557
	movh.a	a4,#@his(_27)
	lea	a4,[a4]@los(_27)
	callg	TC1775_ASC0_printf
;  558 |
;  559 |// 	P10DIR = 1; //LED on
;  560 |
;  561 |TC1775_ASC0_printf("Sieve Benchmark at 40MHz CPU-Speed\n\r");
	.symb	LINE, 561
	movh.a	a4,#@his(_28)
	lea	a4,[a4]@los(_28)
	callg	TC1775_ASC0_printf
;  562 |for(count=0; count<=4; count++)
	.symb	LINE, 562
	mov16	d15,#0				; count
	st.b	count,d15			; count
	j	_40
_39:
;  563 |	{
;  564 |	sieve();
	.symb	LINE, 564
	callg	sieve
;  565 |	P10DIR = ~P10DIR; // toggle LED
	.symb	LINE, 565
	ld.w	d15,-268422632
	xnor	d15,d15,#0
	st.w	-268422632,d15
	.symb	LINE, 562
	ld.bu	d15,count			; count
	add16	d15,#1				; count
	st.b	count,d15			; count
_40:
	ld.bu	d15,count			; count
	jlt	d15,#5,_39
;  566 |	}
;  567 |
;  568 |
;  569 |TC1775_ASC0_printf("----- with instruction-cache enabled\n\r");
	.symb	LINE, 569
	movh.a	a4,#@his(_29)
	lea	a4,[a4]@los(_29)
	callg	TC1775_ASC0_printf
;  570 |cache_enable();
	.symb	LINE, 570
	callg	cache_enable
;  571 |for(count=0; count<=4; count++)
	.symb	LINE, 571
	mov16	d15,#0				; count
	st.b	count,d15			; count
	j	_42
_41:
;  572 |	{
;  573 |	sieve();
	.symb	LINE, 573
	callg	sieve
;  574 |	P10DIR = ~P10DIR; // toggle LED
	.symb	LINE, 574
	ld.w	d15,-268422632
	xnor	d15,d15,#0
	st.w	-268422632,d15
	.symb	LINE, 571
	ld.bu	d15,count			; count
	add16	d15,#1				; count
	st.b	count,d15			; count
_42:
	ld.bu	d15,count			; count
	jlt	d15,#5,_41
;  575 |	}
;  576 |cache_disable();
	.symb	LINE, 576
	callg	cache_disable
;  577 |
;  578 |
;  579 |TC1775_ASC0_printf("----- with burst-mode enabled\n\r");
	.symb	LINE, 579
	movh.a	a4,#@his(_30)
	lea	a4,[a4]@los(_30)
	callg	TC1775_ASC0_printf
;  580 |if (switch_to_IFU())
	.symb	LINE, 580
	callg	switch_to_IFU
	jeq	d2,#0,_45
;  581 |	{ 
;  582 |//	TC1775_ASC0_printf("		burst-mode enabled successfuly\n\r");
;  583 |	for(count=0; count<=4; count++)
	.symb	LINE, 583
	mov16	d15,#0				; count
	st.b	count,d15			; count
	j	_44
_43:
;  584 |		{
;  585 |		sieve();
	.symb	LINE, 585
	callg	sieve
;  586 |		P10DIR = ~P10DIR; //toggle LED 
	.symb	LINE, 586
	ld.w	d15,-268422632
	xnor	d15,d15,#0
	st.w	-268422632,d15
	.symb	LINE, 583
	ld.bu	d15,count			; count
	add16	d15,#1				; count
	st.b	count,d15			; count
_44:
	ld.bu	d15,count			; count
	jlt	d15,#5,_43
;  587 |		}
;  588 |	}
	.symb	LINE, 588
	j	_46
_45:
;  589 |else 
;  590 |	TC1775_ASC0_printf("		failed to enable burst-mode :-( \n\r");
	.symb	LINE, 590
	movh.a	a4,#@his(_31)
	lea	a4,[a4]@los(_31)
	callg	TC1775_ASC0_printf
_46:
;  591 |
;  592 |//_debug();
;  593 |while (1);
	.symb	LINE, 593
	j	_48
_47:
_48:
_49:
	j	_49
;  594 |
;  595 |  // USER CODE END
;  596 |
;  597 |} //  End of function main
	.symb	LINE, 597
	ret16
	.symb	EFUN
;  598 |
;  599 |
;  600 |
;  601 |// USER CODE BEGIN (MAIN_General,10)
;  602 |
;  603 |// USER CODE END
;  604 |
	.symb	ENDF
	.sdecl	"fardata.main",DATA,INIT
	.sect	"fardata.main"
	.align	4
_31:
	.ascii	"		failed to enable burst-mode :-( "
	.byte	0x0a,0x0d,0x00
	.align	2
_30:
	.ascii	"----- with burst-mode enabled"
	.byte	0x0a,0x0d,0x00
	.symb	TYPE, 310, 'X', 8, #1, 26, 0
	.symb	ALAB, ASC0_vInit, #310
	.symb	TYPE, 311, 'X', 8, #16, 26, 3, #260, #260, #260
	.symb	ALAB, vsprintf, #311
_28:
	.ascii	"Sieve Benchmark at 40MHz CPU-Speed"
	.byte	0x0a,0x0d,0x00
	.symb	TYPE, 312, 'X', 8, #18, 26, 0
	.symb	ALAB, switch_to_IFU, #312
	.align	2
_27:
	.byte	0x0a,0x0d
	.ascii	"Burst Mode Demo Tricore TC1775"
	.byte	0x0a,0x0d,0x00
	.symb	TYPE, 313, 'X', 8, #1, 26, 0
	.symb	ALAB, cache_disable, #313
	.symb	TYPE, 314, 'X', 8, #1, 26, 0
	.symb	ALAB, sieve, #314
	.symb	TYPE, 315, 'X', 8, #1, 26, 0
	.symb	ALAB, cache_enable, #315
	.symb	TYPE, 316, 'Z', #2, 79
	.symb	IDEN, "buffer", buffer, #316, 129, 0x0
	.symb	ALAB, buffer, #316
	.sdecl	"farbss.main",DATA,CLEAR
	.sect	"farbss.main"
	.align	4
buffer:
	.space	80
	.sect	"fardata.main"
	.align	2
_29:
	.ascii	"----- with instruction-cache enabled"
	.byte	0x0a,0x0d,0x00
	.symb	TYPE, 318, 'X', 8, #1, 26, 1, #5
	.symb	ALAB, ASC0_vSendData, #318
	.symb	IDEN, "count", count, #3, 131, 0x0
	.symb	ALAB, count, #3
	.sdecl	"bss.main",DATA,CLEAR,ABS18
	.sect	"bss.main"
	.align	4
count:
	.space	1
	.sect	"fardata.main"
	.align	4
	.sect	"bss.main"
	.align	4
	.global	MAIN_vInit
	.global	MAIN_vWriteWDTCON0
	.global	TC1775_ASC0_printf
	.global	buffer
	.global	count
	.global	main
	.extern	(CODE) ASC0_vInit
	.extern	(CODE) ASC0_vSendData
	.extern	_START
	.extern	(DATA) _lc_ub_xvwbuffer
	.extern	(DATA) _lc_ue_xvwbuffer
	.extern	(CODE) cache_disable
	.extern	(CODE) cache_enable
	.extern	(CODE) sieve
	.extern	(CODE) switch_to_IFU
	.extern	(CODE) vsprintf
	.calls	"MAIN_vInit", "ASC0_vInit"
	.calls	"MAIN_vInit", "MAIN_vWriteWDTCON0"
	.calls	"TC1775_ASC0_printf", "ASC0_vSendData"
	.calls	"TC1775_ASC0_printf", "vsprintf"
	.calls	"main", "MAIN_vInit"
	.calls	"main", "MAIN_vWriteWDTCON0"
	.calls	"main", "TC1775_ASC0_printf"
	.calls	"main", "cache_disable"
	.calls	"main", "cache_enable"
	.calls	"main", "sieve"
	.calls	"main", "switch_to_IFU"
