; TASKING TriCore C compiler v1.5r1 Build 322 SN 00090364
; options: -e -A1 -g -O0 -Id:\ctri\include -s -N8 -zTC112_COR1 -zTC112_COR4
;          -zTC112_COR10 -zTC112_COR13 -zTC112_COR14 -zTC112_COR16 -zTC112_COR17
	.name	"ifu"
	.symb	TOOL, "TASKING TriCore C compiler v1.5", 1
	.symb	TYPE, 256, "bit", 'g', 0, 1
	.symb	FILE, "ifu.c"
; file "ifu.c":
;    1 |/************************************************************************
;    2 |*  FILE        :  IFU.C                                                 *
;    3 |*                                                                       *
;    4 |*  DESCRIPTION :  Switching from FPI to IFU access dependant from Speed *
;    5 |*                                                                       *
;    6 |*  COPYRIGHT   :  (c) 2001 Infineon Technologies                        *
;    7 |*                                                                       *
;    8 |*  AUTHOR      :  Holger Dienst (AI MC AE)                              *
;    9 |*                                                                       *
;   10 |*  VERSION     :  1.03                                                  *
;   11 |*                                                                       *
;   12 |*  CHANGES     :  includes selection between A/B Step of TC1775         *
;   13 |*                 Klaus Scheibert                                       *
;   14 |*		 (SW also executable with Tasking patch -zTC112_DEDECTS)        *
;   15 |*                 														*
;   16 |*  CHANGES     :  Dec 2001 						                        *
;   17 |*                 Bug in function external_switch_program() fixed       *
;   18 |*                 regarding ADDSEL setting						        *
;   19 |************************************************************************/
;   20 |
;   21 |
;   22 |//Phytec:
;   23 |#define TASKING
;   24 |
;   25 |#include "defs\scu.h"
	.symb	FILE, "defs\\scu.h"
	.symb	ENDF
;   26 |#include "defs\pmu.h"
	.symb	FILE, "defs\\pmu.h"
	.symb	ENDF
;   27 |#include "defs\ebua.h"
	.symb	FILE, "defs\\ebua.h"
	.symb	ENDF
;   28 |#include <stdlib.h>
	.symb	FILE, "d:\\ctri\\include\\stdlib.h"
	.symb	TYPE, 257, 'S', 8,\
		 "quot", #16, 0,\
		 "rem", #16, 4
	.symb	TYPE, 258, "div_t", 'T', #257
	.symb	TYPE, 259, 'S', 8,\
		 "quot", #6, 0,\
		 "rem", #6, 4
	.symb	TYPE, 260, "ldiv_t", 'T', #259
	.symb	TYPE, 261, "size_t", 'T', #18
	.symb	TYPE, 262, "wchar_t", 'T', #16
	.symb	ENDF
;   29 |#include "ifu.h"
	.symb	FILE, "ifu.h"
	.symb	ENDF
;   30 |
;   31 |#include "main.h"
	.symb	FILE, "main.h"
	.symb	TYPE, 263, "uword", 'T', #18
	.symb	FILE, "TC1775BRegs.h"
	.symb	ENDF
	.symb	FILE, "ASC0.H"
	.symb	TYPE, 264, "ushort", 'T', #5
	.symb	ENDF
	.symb	ENDF
;   32 |
;   33 |#ifdef GNU
;   34 | #include <machine/intrinsics.h>
;   35 |#endif
;   36 |
;   37 |/* defines use to detect the flash type */
;   38 |#define	SETUP_ADR	0x0555 * 4
;   39 |#define	UNLOCK_ADR	0x02AA * 4
;   40 |
;   41 |#define	AMDSET_UP     	0x00AA00AA
;   42 |#define	AMDUNLOCK     	0x00550055
;   43 |#define	AMDREAD_ID    	0x00900090
;   44 |#define	AMDRESET       	0x00F000F0
;   45 |#define AMDBURST        0x00C000C0
;   46 |#define AMDBURST_ENABLE 0x00010001
;   47 |
;   48 |#define	INTELSET_CFG1   0x00600060
;   49 |#define	INTELSET_CFG2   0x00030003
;   50 |#define	INTELREAD_ARRAY	0x00FF00FF
;   51 |
;   52 |#define	INTEL_LINBURST  0x00000080
;   53 |#define	INTEL_RISCLK    0x00000040
;   54 |#define	INTEL_4BURST    0x00000001
;   55 |#define	INTEL_8BURST    0x00000002
;   56 |#define	INTEL_CBURST    0x00000007
;   57 |
;   58 |
;   59 |#define MANU_ID_AMD       0x0001
;   60 |#define MANU_ID_INTEL     0x0089
;   61 |
;   62 |#define	AM29BL162C_ID	  0x2203
;   63 |#define	AM29BL802C_ID	  0x2281
;   64 |
;   65 |#define	DT28F800F3T_ID	  0x88F1
;   66 |#define	DT28F160F3T_ID	  0x88F3
;   67 |
;   68 |// #define WAITRDC_B_MSK      ((T_Reg32 *) 0xF0000520)->bit7
;   69 |// #define	TC1775A	 	 0x0
;   70 |// this option sets SFR BUSCON0 for A-Step
;   71 |
;   72 |
;   73 |void cache_enable(void)
;   74 |{
	.sdecl	"code.ifu",CODE
	.sect	"code.ifu"
	.align	4
	.symb	LINE, 74
	.symb	TYPE, 265, 'Z', #18, 1
	.symb	TYPE, 267, 'Z', #18, 0
	.symb	TYPE, 269, 'Z', #18, 23
	.symb	TYPE, 271, "pmu", 'S', 128,\
		 "RESERVED0", #265, 0,\
		 "ID", #18, 8,\
		 "RESERVED1", #267, 12,\
		 "CON", #18, 16,\
		 "SFR", #18, 20,\
		 "EIFCON", #18, 24,\
		 "RESERVED2", #267, 28,\
		 "TEST_SFR", #269, 32
	.symb	TYPE, 272, "PMU", 'T', #271
	.symb	TYPE, 273, 'X', 8, #1, 26, 0
	.symb	GFUN, "cache_enable", cache_enable, #273, 0, 16, 0
	.symb	ALAB, cache_enable, #273
cache_enable:
	.symb	SOFF, 16
	.symb	TYPE, 275, 'P', #271
	.symb	IDEN, "psPMU", -16, #275, 131, 0x5
	nop
	sub16.a	sp,#16
;   75 |	PMU	*psPMU;
;   76 |	psPMU = (PMU *)(PMU_BASE);
	.symb	LINE, 76
	movh.a	a15,#0xc800			; -939524352
	lea	a15,[a15]0xffffff00		; -939524352
	st16.a	[sp],a15			; psPMU
;   77 |
;   78 |	psPMU->CON &= ~(PMUCDIS | PMUCBP | PMUDCLS);
	.symb	LINE, 78
	ld16.a	a15,[sp]			; psPMU
	ld.w	d15,[a15]16
	mov16	d7,#-8				; -8
	and16	d15,d7
	st.w	[a15]16,d15			; psPMU
;   79 |	psPMU->CON &= ~(PMUTERF);
	.symb	LINE, 79
	ld16.a	a15,[sp]			; psPMU
	ld.w	d15,[a15]16
	mov	d7,#-17				; -17
	and16	d15,d7
	st.w	[a15]16,d15			; psPMU
;   80 |}
	.symb	LINE, 80
	ret16
	.symb	EFUN
;   81 |
;   82 |void cache_disable(void)
;   83 |{
	.symb	LINE, 83
	.symb	TYPE, 276, 'X', 8, #1, 26, 0
	.symb	GFUN, "cache_disable", cache_disable, #276, 0, 16, 0
	.symb	ALAB, cache_disable, #276
cache_disable:
	.symb	SOFF, 16
	.symb	IDEN, "psPMU", -16, #275, 131, 0x5
	nop
	sub16.a	sp,#16
;   84 |	PMU	*psPMU;
;   85 |	psPMU = (PMU *)(PMU_BASE);
	.symb	LINE, 85
	movh.a	a15,#0xc800			; -939524352
	lea	a15,[a15]0xffffff00		; -939524352
	st16.a	[sp],a15			; psPMU
;   86 |
;   87 |	psPMU->CON |= PMUCBP | PMUDCLS;
	.symb	LINE, 87
	ld16.a	a15,[sp]			; psPMU
	ld.w	d15,[a15]16
	or	d15,d15,#6
	st.w	[a15]16,d15			; psPMU
;   88 |}
	.symb	LINE, 88
	ret16
	.symb	EFUN
;   89 |
;   90 |void external_switch_program(unsigned int uiClockTime)
;   91 |{
	.symb	LINE, 91
	.symb	TYPE, 277, 'Z', #18, 2
	.symb	TYPE, 279, 'Z', #18, 11
	.symb	TYPE, 281, 'Z', #18, 3
	.symb	TYPE, 283, "ebua", 'S', 140,\
		 "CLC", #18, 0,\
		 "RESERVED0", #267, 4,\
		 "ID", #18, 8,\
		 "RESERVED1", #267, 12,\
		 "FBUCON", #18, 16,\
		 "RESERVED2", #277, 20,\
		 "ADDSEL0", #18, 32,\
		 "ADDSEL1", #18, 36,\
		 "ADDSEL2", #18, 40,\
		 "ADDSEL3", #18, 44,\
		 "RESERVED3", #279, 48,\
		 "BUSCON0", #18, 96,\
		 "BUSCON1", #18, 100,\
		 "BUSCON2", #18, 104,\
		 "BUSCON3", #18, 108,\
		 "RESERVED4", #281, 112,\
		 "EMUAS", #18, 128,\
		 "EMUBC", #18, 132,\
		 "EMUCON", #18, 136
	.symb	TYPE, 284, "EBUA", 'T', #283
	.symb	TYPE, 285, 'Z', #18, 5
	.symb	TYPE, 287, "scu", 'S', 124,\
		 "RESERVED0", #265, 0,\
		 "ID", #18, 8,\
		 "RESERVED1", #267, 12,\
		 "RSTREQ", #18, 16,\
		 "RSTSR", #18, 20,\
		 "RESERVED2", #265, 24,\
		 "WDTCON0", #18, 32,\
		 "WDTCON1", #18, 36,\
		 "WDTSR", #18, 40,\
		 "NMISR", #18, 44,\
		 "PMCON", #18, 48,\
		 "PMCSR", #18, 52,\
		 "RESERVED3", #265, 56,\
		 "PLLCLC", #18, 64,\
		 "RESERVED4", #277, 68,\
		 "CON", #18, 80,\
		 "TRSTAT", #18, 84,\
		 "RESERVED5", #285, 88,\
		 "MANID", #18, 112,\
		 "CHIPID", #18, 116,\
		 "RTID", #18, 120
	.symb	TYPE, 288, "SCU", 'T', #287
	.symb	TYPE, 289, 'X', 8, #1, 26, 1, #18
	.symb	GFUN, "external_switch_program", external_switch_program, #289, 0, 64, 0
	.symb	ALAB, external_switch_program, #289
external_switch_program:
	.symb	SOFF, 64
	.symb	LTIM, "uiClockTime", 4, 0, 0x8cd
	.symb	IDEN, "uiClockTime", 4, #18, 0, 0x80d
	.symb	TYPE, 291, 'P', #283
	.symb	IDEN, "psEBUA", -60, #291, 131, 0x5
	.symb	TYPE, 293, 'P', #287
	.symb	IDEN, "psSCU", -56, #293, 131, 0x5
	.symb	IDEN, "psPMU", -52, #275, 131, 0x5
	.symb	TYPE, 295, 'P', #18
	.symb	IDEN, "puiAdr", -48, #295, 131, 0x5
	.symb	IDEN, "uiID", -44, #18, 131, 0x5
	.symb	IDEN, "uiCS0_Base", -40, #18, 131, 0x5
	.symb	IDEN, "uiHWCFGstate", -36, #18, 131, 0x5
	.symb	IDEN, "uiAddr", -32, #18, 131, 0x5
	.symb	IDEN, "uiRDLen", -28, #18, 131, 0x5
	.symb	IDEN, "uiNDiv", -24, #18, 131, 0x5
	.symb	IDEN, "uiWaitStates", -20, #18, 131, 0x5
	.symb	IDEN, "uiTimeToFirstAccess", -16, #18, 131, 0x5
	.symb	LTIM, "uiClockTime", 4, 0, 0x84d
	.symb	LTIM, "uiClockTime", -64, 131, 0x8c5
	.symb	LTIM, "uiClockTime", -64, 131, 0x845
	.symb	LTIM, "uiClockTime", 15, 0, 0x8cd
	.symb	LTIM, "uiClockTime", 15, 0, 0x84d
	nop
	sub16.a	sp,#64
;   92 |    EBUA		*psEBUA;
;   93 |	SCU 		*psSCU;
;   94 |	PMU 		*psPMU;
;   95 |	unsigned int 	*puiAdr;
;   96 |	unsigned int	uiID, uiCS0_Base, uiHWCFGstate, uiAddr;
;   97 |	unsigned int	uiRDLen;
;   98 |	unsigned int 	uiNDiv, uiWaitStates;
;   99 |	unsigned int	uiTimeToFirstAccess;
	.symb	LINE, 99
	st16.w	[sp],d4				; uiClockTime
;  100 |
;  101 |		P10DIR = P10DIR | 0x02; //Eric
	.symb	LINE, 101
	ld.w	d15,-268422632
	or	d15,d15,#2
	st.w	-268422632,d15
;  102 |
;  103 |        psEBUA = (EBUA *)(EBUA_BASE);
	.symb	LINE, 103
	lea	a15,-268434176			; -268434176
	st16.a	[sp]4,a15			; psEBUA
;  104 |       	psSCU = (SCU *)(SCU_BASE);
	.symb	LINE, 104
	lea	a15,-268435456			; -268435456
	st16.a	[sp]8,a15			; psSCU
;  105 |       	psPMU = (PMU *)(PMU_BASE);
	.symb	LINE, 105
	movh.a	a15,#0xc800			; -939524352
	lea	a15,[a15]0xffffff00		; -939524352
	st16.a	[sp]12,a15			; psPMU
;  106 |
;  107 |	/* get the baseaddress of flash */
;  108 |	uiCS0_Base = psEBUA->ADDSEL0;
	.symb	LINE, 108
	ld.a	a7,[sp]4			; psEBUA
	ld.w	d15,[a7]32
	st16.w	[sp]24,d15			; uiCS0_Base
;  109 |	uiCS0_Base &= BASE_MSK;
	.symb	LINE, 109
	ld16.w	d15,[sp]24			; uiCS0_Base
	mov	d7,#-4096			; -4096
	and16	d15,d7				; uiCS0_Base
	st16.w	[sp]24,d15			; uiCS0_Base
;  110 |
;  111 |	/* calculate time to first access for burst read (3 -> 3ns setup to clk */
;  112 |	uiTimeToFirstAccess = 2*uiClockTime-3;
	.symb	LINE, 112
	ld16.w	d15,[sp]			; uiClockTime
	sh16	d15,#1
	add16	d15,#-3
	st16.w	[sp]48,d15			; uiTimeToFirstAccess
;  113 |	uiRDLen = 0;
	.symb	LINE, 113
	mov16	d15,#0				; uiRDLen
	st16.w	[sp]36,d15			; uiRDLen
;  114 |	while (uiTimeToFirstAccess<FLASH_FIRST_ACCESS_TIME)
	.symb	LINE, 114
	j	_18
_17:
	.symb	LTIM, "uiClockTime", 7, 0, 0x8cd
;  115 |	{
;  116 |		uiRDLen++;
	.symb	LINE, 116
	nop
	ld16.w	d15,[sp]36			; uiRDLen
	add16	d15,#1				; uiRDLen
	st16.w	[sp]36,d15			; uiRDLen
;  117 |		uiTimeToFirstAccess += uiClockTime;
	.symb	LINE, 117
	ld16.w	d15,[sp]48			; uiTimeToFirstAccess
	ld16.w	d7,[sp]				; uiClockTime
	add16	d15,d7				; uiTimeToFirstAccess
	st16.w	[sp]48,d15			; uiTimeToFirstAccess
	.symb	LINE, 114
_18:
	.symb	LTIM, "uiClockTime", 7, 0, 0x84d
	.symb	LTIM, "uiClockTime", 15, 0, 0x8cd
	.symb	LTIM, "uiClockTime", 15, 0, 0x84d
	nop
	ld16.w	d15,[sp]48			; uiTimeToFirstAccess
	lt.u	d15,d15,#65
	jne	d15,#0,_17
;  118 |	}
;  119 |	/* calculate time to first access for asynchronous read (7ns delay from clk+7ns setup to clk */
;  120 |	uiTimeToFirstAccess = uiClockTime/2-7;
	.symb	LINE, 120
	ld16.w	d15,[sp]			; uiClockTime
	sh16	d15,#-1
	add16	d15,#-7
	st16.w	[sp]48,d15			; uiTimeToFirstAccess
;  121 |	uiWaitStates = 0;
	.symb	LINE, 121
	mov16	d15,#0				; uiWaitStates
	st16.w	[sp]44,d15			; uiWaitStates
;  122 |	while (uiTimeToFirstAccess<FLASH_FIRST_ACCESS_TIME)
	.symb	LINE, 122
	j	_20
_19:
	.symb	LTIM, "uiClockTime", 7, 0, 0x8cd
;  123 |	{
;  124 |		uiWaitStates++;
	.symb	LINE, 124
	nop
	ld16.w	d15,[sp]44			; uiWaitStates
	add16	d15,#1				; uiWaitStates
	st16.w	[sp]44,d15			; uiWaitStates
;  125 |		uiTimeToFirstAccess += uiClockTime;
	.symb	LINE, 125
	ld16.w	d15,[sp]48			; uiTimeToFirstAccess
	ld16.w	d7,[sp]				; uiClockTime
	add16	d15,d7				; uiTimeToFirstAccess
	st16.w	[sp]48,d15			; uiTimeToFirstAccess
	.symb	LINE, 122
_20:
	.symb	LTIM, "uiClockTime", 7, 0, 0x84d
	nop
	ld16.w	d15,[sp]48			; uiTimeToFirstAccess
	lt.u	d15,d15,#65
	jne	d15,#0,_19
;  126 |	}
;  127 |
;  128 |	puiAdr = (unsigned int *)(uiCS0_Base + SETUP_ADR);
	.symb	LINE, 128
	ld16.w	d15,[sp]24			; uiCS0_Base
	addi	d15,d15,#5460
	mov16.a	a15,d15
	st16.a	[sp]16,a15			; puiAdr
;  129 |	*puiAdr = AMDSET_UP;
	.symb	LINE, 129
	ld.a	a7,[sp]16			; puiAdr
	mov.u	d15,#0xaa			; 11141290
	addih	d15,d15,#0xaa			; 11141290
	st16.w	[a7],d15			; puiAdr
;  130 |
;  131 |	puiAdr = (unsigned int *)(uiCS0_Base + UNLOCK_ADR);
	.symb	LINE, 131
	ld16.w	d15,[sp]24			; uiCS0_Base
	addi	d15,d15,#2728
	mov16.a	a15,d15
	st16.a	[sp]16,a15			; puiAdr
;  132 |	*puiAdr = AMDUNLOCK;
	.symb	LINE, 132
	ld.a	a7,[sp]16			; puiAdr
	mov.u	d15,#0x55			; 5570645
	addih	d15,d15,#0x55			; 5570645
	st16.w	[a7],d15			; puiAdr
;  133 |
;  134 |	puiAdr = (unsigned int *)(uiCS0_Base + SETUP_ADR);
	.symb	LINE, 134
	ld16.w	d15,[sp]24			; uiCS0_Base
	addi	d15,d15,#5460
	mov16.a	a15,d15
	st16.a	[sp]16,a15			; puiAdr
;  135 |	*puiAdr = AMDREAD_ID;
	.symb	LINE, 135
	ld.a	a7,[sp]16			; puiAdr
	mov.u	d15,#0x90			; 9437328
	addih	d15,d15,#0x90			; 9437328
	st16.w	[a7],d15			; puiAdr
;  136 |
;  137 |	puiAdr = (unsigned int *)(uiCS0_Base + 0);
	.symb	LINE, 137
	ld16.w	d15,[sp]24			; uiCS0_Base
	mov16.a	a15,d15				; uiCS0_Base
	st16.a	[sp]16,a15			; puiAdr
;  138 |	uiID = *puiAdr << 16;
	.symb	LINE, 138
	ld.a	a7,[sp]16			; puiAdr
	ld16.w	d15,[a7]
	sh	d15,d15,#16
	st16.w	[sp]20,d15			; uiID
;  139 |
;  140 |	puiAdr = (unsigned int *)(uiCS0_Base + 4);
	.symb	LINE, 140
	ld16.w	d15,[sp]24			; uiCS0_Base
	add16	d15,#4
	mov16.a	a15,d15
	st16.a	[sp]16,a15			; puiAdr
;  141 |	uiID |= *puiAdr	& 0x0000FFFF;
	.symb	LINE, 141
	ld16.w	d15,[sp]20			; uiID
	ld.a	a7,[sp]16			; puiAdr
	ld16.w	d7,[a7]
	mov.u	d6,#65535			; 65535
	and16	d7,d6
	or16	d15,d7				; uiID
	st16.w	[sp]20,d15			; uiID
;  142 |
;  143 |	*puiAdr = AMDRESET;
	.symb	LINE, 143
	ld.a	a7,[sp]16			; puiAdr
	mov.u	d15,#0xf0			; 15728880
	addih	d15,d15,#0xf0			; 15728880
	st16.w	[a7],d15			; puiAdr
;  144 |
;  145 |	switch (uiID & 0xFFFF)
	.symb	LINE, 145
	ld16.w	d15,[sp]20			; uiID
	mov.u	d7,#65535			; 65535
	and16	d15,d7
	addi	d15,d15,#-8707
	jeq	d15,#0,_24			; case 8707
	addi	d15,d15,#-126
	jeq	d15,#0,_21			; case 8833
	addi	d15,d15,#-26226
	jeq	d15,#-2,_22			; case 35057
	jeq	d15,#0,_23			; case 35059
	j	_25				; default
;  146 |	{
;  147 |		case AM29BL802C_ID :
	.symb	LINE, 147
_21:
;  148 |		case DT28F800F3T_ID:
	.symb	LINE, 148
_22:
;  149 |				     break;
	.symb	LINE, 149
	j	_27
;  150 |		case DT28F160F3T_ID:
	.symb	LINE, 150
_23:
;  151 |		case AM29BL162C_ID :
	.symb	LINE, 151
_24:
;  152 |				     psEBUA->ADDSEL0 = (psEBUA->ADDSEL0 & ~(MASK_MSK)) | MASK_4MB;
	.symb	LINE, 152
	nop
	ld.a	a7,[sp]4			; psEBUA
	ld.w	d15,[a7]32
	mov	d7,#-241			; -241
	and16	d15,d7
	or	d15,d15,#80
	ld.a	a7,[sp]4			; psEBUA
	st.w	[a7]32,d15			; psEBUA
;  153 |				     break;
	.symb	LINE, 153
	j	_27
;  154 |		default:
	.symb	LINE, 154
_25:
;  155 |		         uiID = 0;
	.symb	LINE, 155
	mov16	d15,#0				; uiID
	st16.w	[sp]20,d15			; uiID
;  156 |				     break;
;  157 |	}
	.symb	LINE, 157
_27:
;  158 |	// if we found no burst device or bottom boot (Intel) then no switching
;  159 |	if (!uiID) return;
	.symb	LINE, 159
	nop
	ld16.w	d15,[sp]20			; uiID
	jne	d15,#0,_28			; uiID
	ret16
_28:
;  160 |
;  161 |	// setting waitstates for different flash's
;  162 |	if ((uiID>>16) == MANU_ID_AMD)
	.symb	LINE, 162
	nop
	ld16.w	d15,[sp]20			; uiID
	sh	d15,d15,#-16
	jne	d15,#1,_30
;  163 |	{
;  164 |		// enable burst on the flash
;  165 |		puiAdr = (unsigned int *)(uiCS0_Base + SETUP_ADR);
	.symb	LINE, 165
	ld16.w	d15,[sp]24			; uiCS0_Base
	addi	d15,d15,#5460
	mov16.a	a15,d15
	st16.a	[sp]16,a15			; puiAdr
;  166 |		*puiAdr = AMDSET_UP;
	.symb	LINE, 166
	ld.a	a7,[sp]16			; puiAdr
	mov.u	d15,#0xaa			; 11141290
	addih	d15,d15,#0xaa			; 11141290
	st16.w	[a7],d15			; puiAdr
;  167 |
;  168 |		puiAdr = (unsigned int *)(uiCS0_Base + UNLOCK_ADR);
	.symb	LINE, 168
	ld16.w	d15,[sp]24			; uiCS0_Base
	addi	d15,d15,#2728
	mov16.a	a15,d15
	st16.a	[sp]16,a15			; puiAdr
;  169 |		*puiAdr = AMDUNLOCK;
	.symb	LINE, 169
	ld.a	a7,[sp]16			; puiAdr
	mov.u	d15,#0x55			; 5570645
	addih	d15,d15,#0x55			; 5570645
	st16.w	[a7],d15			; puiAdr
;  170 |
;  171 |		puiAdr = (unsigned int *)(uiCS0_Base + SETUP_ADR);
	.symb	LINE, 171
	ld16.w	d15,[sp]24			; uiCS0_Base
	addi	d15,d15,#5460
	mov16.a	a15,d15
	st16.a	[sp]16,a15			; puiAdr
;  172 |		*puiAdr = AMDBURST;
	.symb	LINE, 172
	ld.a	a7,[sp]16			; puiAdr
	mov.u	d15,#0xc0			; 12583104
	addih	d15,d15,#0xc0			; 12583104
	st16.w	[a7],d15			; puiAdr
;  173 |
;  174 |		puiAdr = (unsigned int *)(uiCS0_Base);
	.symb	LINE, 174
	ld16.w	d15,[sp]24			; uiCS0_Base
	mov16.a	a15,d15				; uiCS0_Base
	st16.a	[sp]16,a15			; puiAdr
;  175 |		*puiAdr = AMDBURST_ENABLE;
	.symb	LINE, 175
	ld.a	a7,[sp]16			; puiAdr
	mov.u	d15,#0x1			; 65537
	addih	d15,d15,#0x1			; 65537
	st16.w	[a7],d15			; puiAdr
;  176 |
;  177 |		*puiAdr = AMDRESET;
	.symb	LINE, 177
	ld.a	a7,[sp]16			; puiAdr
	mov.u	d15,#0xf0			; 15728880
	addih	d15,d15,#0xf0			; 15728880
	st16.w	[a7],d15			; puiAdr
;  178 |		// clear waitstates
;  179 |		#ifdef TC1775A   // TC1775 A-Step
;  180 |		  psEBUA->BUSCON0 &= ~(WAITRDC_A_MSK | WAITWRC_A_MSK | CMULT_MSK );
;  181 |		#else          // TC1775 B-Step
;  182 |		  psEBUA->BUSCON0 &= ~(WAITRDC_B_MSK | WAITWRC_B_MSK | CMULT_MSK | CMULTR_MSK);
	.symb	LINE, 182
	ld16.a	a15,[sp]4			; psEBUA
	ld.w	d15,[a15]96
	mov.u	d7,#0x83c			; -12646340
	addih	d7,d7,#0xff3f			; -12646340
	and16	d15,d7
	st.w	[a15]96,d15			; psEBUA
;  183 |		#endif
;  184 |		// setting EIFCON
;  185 |		psPMU->EIFCON = (uiRDLen<<1) | PMUFBBMSEL | PMUFBBLEN_32 | IFU_BLEN | PMUWAITFUNC;
	.symb	LINE, 185
	ld16.w	d15,[sp]36			; uiRDLen
	sh16	d15,#1
	mov	d7,#3680			; 3680
	or16	d15,d7
	ld.a	a7,[sp]12			; psPMU
	st.w	[a7]24,d15			; psPMU
;  186 |//		psPMU->EIFCON = 0x00000E61; //PHYTEC
;  187 |
;  188 |		if (uiWaitStates>3)
	.symb	LINE, 188
	ld16.w	d15,[sp]44			; uiWaitStates
	jlt.u	d15,#4,_29
;  189 |		{
;  190 |			// setting cmult for different flash's
;  191 |			psEBUA->BUSCON0 |= CMULT_CM4;
	.symb	LINE, 191
	ld16.a	a15,[sp]4			; psEBUA
	ld.w	d15,[a15]96
	or	d15,d15,#1
	st.w	[a15]96,d15			; psEBUA
;  192 |			uiWaitStates -= 3;
	.symb	LINE, 192
	ld16.w	d15,[sp]44			; uiWaitStates
	add16	d15,#-3				; uiWaitStates
	st16.w	[sp]44,d15			; uiWaitStates
;  193 |		}
	.symb	LINE, 193
_29:
;  194 |		// setting waitstates for different flash's
;  195 |		#ifdef TC1775A		// TC1775 A-Step
;  196 |		 psEBUA->BUSCON0 |= (uiWaitStates<<6) | (uiWaitStates<<8);
;  197 |       		#else           // TC1775 B-Step
;  198 |        	 psEBUA->BUSCON0 |= (uiWaitStates<<6) | (uiWaitStates<<9);
	.symb	LINE, 198
	nop
	ld16.a	a15,[sp]4			; psEBUA
	ld.w	d15,[a15]96
	ld.w	d7,[sp]44			; uiWaitStates
	sh16	d7,#6
	ld.w	d6,[sp]44			; uiWaitStates
	sh	d6,d6,#9
	or16	d7,d6
	or16	d15,d7
	st.w	[a15]96,d15			; psEBUA
;  199 |		#endif
;  200 |
;  201 |	}
	.symb	LINE, 201
	j	_36
_30:
;  202 |	else
;  203 |	{
;  204 |		// calculate Address for configuration
;  205 |		uiAddr = (uiWaitStates-1)<<11;
	.symb	LINE, 205
	nop
	ld16.w	d15,[sp]44			; uiWaitStates
	add16	d15,#-1
	sh	d15,d15,#11
	st16.w	[sp]32,d15			; uiAddr
;  206 |		uiAddr |= INTEL_LINBURST;
	.symb	LINE, 206
	ld16.w	d15,[sp]32			; uiAddr
	or	d15,d15,#128			; uiAddr
	st16.w	[sp]32,d15			; uiAddr
;  207 |		uiAddr |= INTEL_RISCLK;
	.symb	LINE, 207
	ld16.w	d15,[sp]32			; uiAddr
	or	d15,d15,#64			; uiAddr
	st16.w	[sp]32,d15			; uiAddr
;  208 |		uiAddr |= INTEL_BLEN;
	.symb	LINE, 208
	ld16.w	d15,[sp]32			; uiAddr
	or	d15,d15,#2			; uiAddr
	st16.w	[sp]32,d15			; uiAddr
;  209 |
;  210 |		// enable burst on the flash
;  211 |		puiAdr = (unsigned int *)(uiCS0_Base + (uiAddr<<2));
	.symb	LINE, 211
	ld16.w	d15,[sp]24			; uiCS0_Base
	ld.w	d7,[sp]32			; uiAddr
	sh16	d7,#2
	add16	d15,d7
	mov16.a	a15,d15
	st16.a	[sp]16,a15			; puiAdr
;  212 |		*puiAdr = INTELSET_CFG1;
	.symb	LINE, 212
	ld.a	a7,[sp]16			; puiAdr
	mov.u	d15,#0x60			; 6291552
	addih	d15,d15,#0x60			; 6291552
	st16.w	[a7],d15			; puiAdr
;  213 |		*puiAdr = INTELSET_CFG2;
	.symb	LINE, 213
	ld.a	a7,[sp]16			; puiAdr
	mov.u	d15,#0x3			; 196611
	addih	d15,d15,#0x3			; 196611
	st16.w	[a7],d15			; puiAdr
;  214 |		*puiAdr = INTELREAD_ARRAY;
	.symb	LINE, 214
	ld.a	a7,[sp]16			; puiAdr
	mov.u	d15,#0xff			; 16711935
	addih	d15,d15,#0xff			; 16711935
	st16.w	[a7],d15			; puiAdr
;  215 |
;  216 |		// clear waitstates
;  217 |		#ifdef TC1775A   // TC1775 A-Step
;  218 |		 psEBUA->BUSCON0 &= ~(WAITRDC_A_MSK | WAITWRC_A_MSK | CMULT_MSK);
;  219 |		#else          // TC1775 B-Step
;  220 |		  psEBUA->BUSCON0 &= ~(WAITRDC_B_MSK | WAITWRC_B_MSK | CMULT_MSK | CMULTR_MSK);
	.symb	LINE, 220
	ld16.a	a15,[sp]4			; psEBUA
	ld.w	d15,[a15]96
	mov.u	d7,#0x83c			; -12646340
	addih	d7,d7,#0xff3f			; -12646340
	and16	d15,d7
	st.w	[a15]96,d15			; psEBUA
;  221 |		#endif
;  222 |		// setting EIFCON
;  223 |		psPMU->EIFCON = (uiRDLen<<1) | PMUFBBMSEL | INTEL_FBBLEN | IFU_BLEN;
	.symb	LINE, 223
	ld16.w	d15,[sp]36			; uiRDLen
	sh16	d15,#1
	mov	d7,#3392			; 3392
	or16	d15,d7
	ld.a	a7,[sp]12			; psPMU
	st.w	[a7]24,d15			; psPMU
;  224 |		if (uiWaitStates>3)
	.symb	LINE, 224
	ld16.w	d15,[sp]44			; uiWaitStates
	jlt.u	d15,#4,_31
;  225 |		{
;  226 |			// setting cmult for different flash's
;  227 |			psEBUA->BUSCON0 |= CMULT_CM4;
	.symb	LINE, 227
	ld16.a	a15,[sp]4			; psEBUA
	ld.w	d15,[a15]96
	or	d15,d15,#1
	st.w	[a15]96,d15			; psEBUA
;  228 |			uiWaitStates -= 3;
	.symb	LINE, 228
	ld16.w	d15,[sp]44			; uiWaitStates
	add16	d15,#-3				; uiWaitStates
	st16.w	[sp]44,d15			; uiWaitStates
;  229 |		}
	.symb	LINE, 229
_31:
;  230 |		// setting waitstates for different flash's
;  231 |		uiNDiv = (((psSCU->PLLCLC)>>12) & 0x7)+8;
	.symb	LINE, 231
	nop
	ld.a	a7,[sp]8			; psSCU
	ld.w	d15,[a7]64
	sh	d15,d15,#-12
	and	d15,d15,#7
	addi	d15,d15,#8
	st16.w	[sp]40,d15			; uiNDiv
;  232 |
;  233 |		#ifdef TC1775A   // TC1775 A-Step
;  234 |	 		if (uiNDiv < 3) psEBUA->BUSCON0 |= (2<<6) | (2<<8);
;  235 |			else if (uiNDiv < 4) psEBUA->BUSCON0 |= (3<<6) | (3<<8);
;  236 |			     else psEBUA->BUSCON0 |= (1<<6) | (1<<8);
;  237 |		#else          // TC1775 B-Step
;  238 |	 		if (uiNDiv < 3) psEBUA->BUSCON0 |= (2<<6) | (2<<9);
	.symb	LINE, 238
	ld16.w	d15,[sp]40			; uiNDiv
	jge.u	d15,#3,_32
	ld16.a	a15,[sp]4			; psEBUA
	ld.w	d15,[a15]96
	mov	d7,#1152			; 1152
	or16	d15,d7
	st.w	[a15]96,d15			; psEBUA
	j	_35
_32:
;  239 |			else if (uiNDiv < 4) psEBUA->BUSCON0 |= (3<<6) | (3<<9);
	.symb	LINE, 239
	nop
	ld16.w	d15,[sp]40			; uiNDiv
	jge.u	d15,#4,_33
	ld16.a	a15,[sp]4			; psEBUA
	ld.w	d15,[a15]96
	mov	d7,#1728			; 1728
	or16	d15,d7
	st.w	[a15]96,d15			; psEBUA
	j	_34
_33:
;  240 |			     else psEBUA->BUSCON0 |= (1<<6) | (1<<9);
	.symb	LINE, 240
	nop
	ld16.a	a15,[sp]4			; psEBUA
	ld.w	d15,[a15]96
	mov	d7,#576				; 576
	or16	d15,d7
	st.w	[a15]96,d15			; psEBUA
_34:
_35:
;  241 |		#endif
;  242 |
;  243 |	}
	.symb	LINE, 243
_36:
;  244 |
;  245 |	// set rfb terminate on new miss with Burstlength 1 and 2, clear rfb terminate with Burstlength 4 and 8
;  246 |	if (psPMU->EIFCON & PMUIFUBLEN_8) psPMU->CON &= ~PMUTERF;
	.symb	LINE, 246
	nop
	ld.a	a7,[sp]12			; psPMU
	ld.w	d15,[a7]24
	mov	d7,#3072			; 3072
	and16	d15,d7
	jeq	d15,#0,_37
	ld16.a	a15,[sp]12			; psPMU
	ld.w	d15,[a15]16
	mov	d7,#-17				; -17
	and16	d15,d7
	st.w	[a15]16,d15			; psPMU
	j	_38
_37:
;  247 |	else psPMU->CON |= PMUTERF;
	.symb	LINE, 247
	nop
	ld16.a	a15,[sp]12			; psPMU
	ld.w	d15,[a15]16
	or	d15,d15,#16
	st.w	[a15]16,d15			; psPMU
_38:
;  248 |	// set waitstates between cycles to 0
;  249 |	psPMU->CON &= ~PMUSEWC_7;
	.symb	LINE, 249
	nop
	ld16.a	a15,[sp]12			; psPMU
	ld.w	d15,[a15]16
	mov	d7,#-14337			; -14337
	and16	d15,d7
	st.w	[a15]16,d15			; psPMU
;  250 |
;  251 |	// switch to IFU if is nessecary
;  252 |	uiHWCFGstate = psSCU->RSTSR & HWCFG_MSK;
	.symb	LINE, 252
	ld.a	a7,[sp]8			; psSCU
	ld.w	d15,[a7]20
	movh	d7,#0xf				; 983040
	and16	d15,d7
	st16.w	[sp]28,d15			; uiHWCFGstate
;  253 |	uiHWCFGstate >>= 16;
	.symb	LINE, 253
	ld16.w	d15,[sp]28			; uiHWCFGstate
	sh	d15,d15,#-16			; uiHWCFGstate
	st16.w	[sp]28,d15			; uiHWCFGstate
;  254 |	if ((uiHWCFGstate != 0x4) && (uiHWCFGstate != 0xC))
	.symb	LINE, 254
	ld16.w	d15,[sp]28			; uiHWCFGstate
	jeq	d15,#4,_40
	ld16.w	d15,[sp]28			; uiHWCFGstate
	ne	d15,d15,#12
	jeq	d15,#0,_40
;  255 |	{
;  256 |		// switch to IFU
;  257 |	psSCU->CON |= EXTIF | ENSWIF | EBUEN;
	.symb	LINE, 257
	ld16.a	a15,[sp]8			; psSCU
	ld.w	d15,[a15]80
	mov.u	d7,#33536			; 33536
	or16	d15,d7
	st.w	[a15]80,d15			; psSCU
;  258 |	}
	.symb	LINE, 258
_40:
;  259 |
;  260 |#ifdef GREEN_HILLS
;  261 |	__isync();
;  262 |	__dsync();
;  263 |#else
;  264 |	_isync();
	.symb	LINE, 264
	isync
;  265 |	_dsync();
	.symb	LINE, 265
	dsync
;  266 |#endif
;  267 |
;  268 |}
	.symb	LINE, 268
_41:
	ret16
	.symb	EFUN
;  269 |
;  270 |// calling function indirectly
;  271 |#ifdef GREEN_HILLS
;  272 |void asm
;  273 |indcall( puiDestination )
;  274 |{
;  275 |%areg puiDestination
;  276 |    calli	puiDestination
;  277 |%error
;  278 |}
;  279 |#endif
;  280 |
;  281 |// calling function indirectly for GNU
;  282 |#ifdef GNU
;  283 |void indcall(uiClockTime)
;  284 |{
;  285 | asm volatile ("calli %a4");
;  286 |}
;  287 |#endif
;  288 |
;  289 |unsigned int switch_to_IFU(void)
;  290 |{
	.symb	LINE, 290
	.symb	TYPE, 296, 'X', 8, #18, 26, 0
	.symb	GFUN, "switch_to_IFU", switch_to_IFU, #296, 0, 32, 0
	.symb	ALAB, switch_to_IFU, #296
switch_to_IFU:
	.symb	SOFF, 32
	.symb	IDEN, "psSCU", -32, #293, 131, 0x5
	.symb	IDEN, "uiNDiv", -28, #18, 131, 0x5
	.symb	IDEN, "uiKDiv", -24, #18, 131, 0x5
	.symb	IDEN, "uiClockTime", -20, #18, 131, 0x5
	.symb	IDEN, "uiFrequency", -16, #18, 131, 0x5
	.symb	IDEN, "puiSource", -12, #295, 131, 0x5
	.symb	IDEN, "puiDestination", -8, #295, 131, 0x5
	.symb	IDEN, "puiDataHeap", -4, #295, 131, 0x5
	nop
	sub16.a	sp,#32
;  291 |	SCU 		*psSCU;
;  292 |
;  293 |    unsigned int 	uiNDiv, uiKDiv, uiClockTime, uiFrequency;
;  294 |    unsigned int	*puiSource;
;  295 |	unsigned int	*puiDestination;
;  296 |	unsigned int 	*puiDataHeap;
;  297 |
;  298 |    psSCU = (SCU *)(SCU_BASE);
	.symb	LINE, 298
	lea	a15,-268435456			; -268435456
	st16.a	[sp],a15			; psSCU
;  299 |
;  300 |	puiDataHeap = malloc((unsigned int)&switch_to_IFU-(unsigned int)&external_switch_program);
	.symb	LINE, 300
	movh.a	a15,#@his(switch_to_IFU)
	lea	a15,[a15]@los(switch_to_IFU)
	mov16.d	d4,a15
	movh.a	a15,#@his(external_switch_program)
	lea	a15,[a15]@los(external_switch_program)
	mov16.d	d15,a15
	sub16	d4,d15
	callg	malloc
	st.a	[sp]28,a2			; puiDataHeap
;  301 |
;  302 |	if (!puiDataHeap) return 0;
	.symb	LINE, 302
	ld.a	a7,[sp]28			; puiDataHeap
	jnz.a	a7,_42				; puiDataHeap
	mov16	d2,#0				; 0
	ret16
_42:
;  303 |	puiDestination = puiDataHeap;
	.symb	LINE, 303
	nop
	ld.a	a7,[sp]28			; puiDataHeap
	st.a	[sp]24,a7			; puiDestination
;  304 |	// first copy all codes to external sram
;  305 |	for(puiSource = (unsigned int *)&external_switch_program;
	.symb	LINE, 305
	movh.a	a15,#@his(external_switch_program)
	lea	a15,[a15]@los(external_switch_program)
	st16.a	[sp]20,a15			; puiSource
	j	_44
_43:
;  306 |		puiSource < (unsigned int *)(&switch_to_IFU); puiSource++)
;  307 |	{
;  308 |		*puiDestination = *puiSource;
	.symb	LINE, 308
	nop
	ld.a	a7,[sp]20			; puiSource
	ld16.w	d15,[a7]
	ld.a	a7,[sp]24			; puiDestination
	st16.w	[a7],d15			; puiDestination
;  309 |		puiDestination++;
	.symb	LINE, 309
	ld.a	a7,[sp]24			; puiDestination
	add16.a	a7,#4				; puiDestination
	st.a	[sp]24,a7			; puiDestination
	.symb	LINE, 306
	ld.a	a7,[sp]20			; puiSource
	add16.a	a7,#4				; puiSource
	st.a	[sp]20,a7			; puiSource
_44:
	nop
	ld.a	a7,[sp]20			; puiSource
	movh.a	a15,#@his(switch_to_IFU)
	lea	a15,[a15]@los(switch_to_IFU)
	lt.a	d15,a7,a15
	jne	d15,#0,_43
;  310 |	}
;  311 |
;  312 |	/* get and calculate the frequency */
;  313 |	uiNDiv = (((psSCU->PLLCLC)>>12) & 0x7)+8;
	.symb	LINE, 313
	ld16.a	a7,[sp]				; psSCU
	ld.w	d15,[a7]64
	sh	d15,d15,#-12
	and	d15,d15,#7
	addi	d15,d15,#8
	st16.w	[sp]4,d15			; uiNDiv
;  314 |	uiKDiv = (((psSCU->PLLCLC)>>16) & 0x7)+2;
	.symb	LINE, 314
	ld16.a	a7,[sp]				; psSCU
	ld.w	d15,[a7]64
	sh	d15,d15,#-16
	and	d15,d15,#7
	add16	d15,#2
	st16.w	[sp]8,d15			; uiKDiv
;  315 |	if (uiKDiv>6) uiKDiv++;
	.symb	LINE, 315
	ld16.w	d15,[sp]8			; uiKDiv
	jlt.u	d15,#7,_45
	ld16.w	d15,[sp]8			; uiKDiv
	add16	d15,#1				; uiKDiv
	st16.w	[sp]8,d15			; uiKDiv
_45:
;  316 |	if (uiKDiv==3) uiKDiv = 16;
	.symb	LINE, 316
	nop
	ld16.w	d15,[sp]8			; uiKDiv
	jne	d15,#3,_46
	mov16	d15,#16				; uiKDiv
	st16.w	[sp]8,d15			; uiKDiv
_46:
;  317 |
;  318 |	/* calculate frequency */
;  319 |	if (psSCU->PLLCLC & BYPASS)
	.symb	LINE, 319
	nop
	ld16.a	a7,[sp]				; psSCU
	ld.w	d15,[a7]64
	mov.u	d7,#32768			; 32768
	and16	d15,d7
	jeq	d15,#0,_49
;  320 |	{
;  321 |		/* we are in VCO Bypass mode ? */
;  322 |		if (uiNDiv > 12) uiFrequency = CRYSTAL_CLOCK/uiKDiv;
	.symb	LINE, 322
	ld16.w	d15,[sp]4			; uiNDiv
	jlt.u	d15,#13,_47
	mov.u	d4,#0x2400			; 16000000
	addih	d4,d4,#0xf4			; 16000000
	ld.w	d5,[sp]8			; uiKDiv
	callg	__rt_udivmod
	st.w	[sp]16,d2			; uiFrequency
	j	_48
_47:
;  323 |		else uiFrequency = CRYSTAL_CLOCK;
	.symb	LINE, 323
	mov.u	d15,#0x2400			; uiFrequency
	addih	d15,d15,#0xf4			; uiFrequency
	st16.w	[sp]16,d15			; uiFrequency
_48:
;  324 |	}
	.symb	LINE, 324
	j	_50
_49:
;  325 |	else uiFrequency = CRYSTAL_CLOCK*uiNDiv/uiKDiv;
	.symb	LINE, 325
	nop
	ld.w	d4,[sp]4			; uiNDiv
	mov.u	d15,#0x2400			; 16000000
	addih	d15,d15,#0xf4			; 16000000
	mul16	d4,d15
	ld.w	d5,[sp]8			; uiKDiv
	callg	__rt_udivmod
	st.w	[sp]16,d2			; uiFrequency
_50:
;  326 |
;  327 |	uiFrequency = uiFrequency/1000000;
	.symb	LINE, 327
	nop
	ld.w	d4,[sp]16			; uiFrequency
	mov.u	d5,#0x4240			; 1000000
	addih	d5,d5,#0xf			; 1000000
	callg	__rt_udivmod
	st.w	[sp]16,d2			; uiFrequency
;  328 |	if (!uiFrequency) uiFrequency++;
	.symb	LINE, 328
	ld16.w	d15,[sp]16			; uiFrequency
	jne	d15,#0,_51			; uiFrequency
	ld16.w	d15,[sp]16			; uiFrequency
	add16	d15,#1				; uiFrequency
	st16.w	[sp]16,d15			; uiFrequency
_51:
	.symb	BGNB, 0, 0
	.symb	TYPE, 298, 'P', #1
	.symb	IDEN, "__tmp_0", -1, #298, 131, 0x5
	.symb	LTIM, "__tmp_0", -1, 0, 0x45
	.symb	LTIM, "__tmp_0", 23, 0, 0xcd
	.symb	IDEN, "__tmp_d4", -1, #16, 131, 0x5
	.symb	LTIM, "__tmp_d4", -1, 0, 0x45
	.symb	LTIM, "__tmp_d4", 4, 0, 0xcd
;  329 |	uiClockTime = 1000/uiFrequency;
	.symb	LINE, 329
	mov	d4,#1000			; 1000
	ld.w	d5,[sp]16			; uiFrequency
	callg	__rt_udivmod
	st.w	[sp]12,d2			; uiClockTime
;  330 |
;  331 |	// jump to external ram
;  332 |	puiDestination = puiDataHeap;
	.symb	LINE, 332
	ld.a	a7,[sp]28			; puiDataHeap
	st.a	[sp]24,a7			; puiDestination
;  333 |
;  334 |	#ifdef GREEN_HILLS
;  335 |     indcall( puiDestination);
;  336 |	#endif
;  337 |
;  338 |	#ifdef TASKING
;  339 |	  // jump to external ram
	.symb	LINE, 339
	ld.a	a7,[sp]24			; puiDestination
	ld.w	d4,[sp]12			; uiClockTime
;  340 |	  #pragma asm(a%0=puiDestination,d4=uiClockTime)
	.symb	LINE, 340
	.symb	LINE, 342
	  calli	a7
;  342 |      #pragma endasm
	.symb	LTIM, "__tmp_d4", 4, 0, 0x4d
	.symb	LTIM, "__tmp_0", 23, 0, 0x4d
	.symb	ENDB
;  343 |	#endif
;  344 |
;  345 |	#ifdef GNU
;  346 |		// jump to external ram
;  347 |		indcall (uiClockTime, puiDestination);
;  348 |	#endif
;  349 |
;  350 |	free(puiDataHeap);
	.symb	LINE, 350
	ld.a	a4,[sp]28			; puiDataHeap
	callg	free
;  351 |
;  352 |	return 1;
	.symb	LINE, 352
	mov16	d2,#1				; 1
;  353 |}
	.symb	LINE, 353
_52:
	ret16
	.symb	EFUN
;  354 |
;  355 |//#endif // GREEN_HILLS
	.symb	ENDF
	.symb	TYPE, 300, 'P', #1
	.symb	TYPE, 301, 'X', 8, #300, 26, 1, #18
	.symb	ALAB, malloc, #301
	.symb	TYPE, 302, 'X', 8, #1, 26, 1, #298
	.symb	ALAB, free, #302
	.global	cache_disable
	.global	cache_enable
	.global	external_switch_program
	.global	switch_to_IFU
	.extern	(CODE) free
	.extern	(CODE) malloc
	.extern	(CODE) __rt_udivmod
	.calls	"switch_to_IFU", "free"
