DAvE's Project Documentation

Project: 		BurstFlash.dav

Controller: 		TC1775 B-Step
Compiler: 		Tasking

Date: 			17.07.2002 12:07:27

Please read this document carefully and note
the red-colored hints.

If you miss a file in the generated files list
maybe you have forgotten to select the
initialisation function of the related module.

Generated Files:
			TC1775BREGS.H
			MAIN.H
			MAIN.C
			ASC0.H
			ASC0.C
			BURSTFLASH.ASM

Project Settings

Macros:

	Macro:
		MAIN_vSetENDINIT()
	Description:
		This macro sets the EndInit bit, which controls access to
		system critical registers. Setting the EndInit bit locks
		all EndInit protected registers.
	Returnvalue:
		None
	Parameters:
		None

	Macro:
		MAIN_vResetENDINIT()
	Description:
		This macro clears the EndInit bit, which controls access to
		system critical registers. Clearing the EndInit bit unlocks
		all EndInit protected registers. Modifications of the
		EndInit bit are monitored by the watchdog timer such that
		after clearing EndInit, the watchdog timer enters a defined
		time-out mode; EndInit must be set again before the
		time-out expires.
	Returnvalue:
		None
	Parameters:
		None
Functions:

	Function:
		void MAIN_vInit(void)
	Description:
		This function initializes the microcontroller.
	Returnvalue:
		None
	Parameters:
		None

	Function:
		void MAIN_vWriteWDTCON0(uword uwValue)
	Description:
		This function writes the parameter uwValue to the WDT_CON0
		register which is password protected.
	Returnvalue:
		None
	Parameters:
		uwValue:
		Value for the WDTCON0 register

	Function:
		void main(void)
	Description:
		This is the main function.
	Returnvalue:
		None
	Parameters:
		None

Initialization:

	Begin of Important Settings for the Start-Up File
	All following settings must be set in the start-up file. You can use
	DAvE's project file (*.dpt) to include this register values into your
	compiler EDE.

	Bus Control Unit (BCU):
	BCU starvation protection is enabled
	BCU power saving is disabled
	the debug trace is enabled. Error information is captured in
	register BCEADD, BCEDAT and BCECON
	sample period of request for starvation protection: 64
	BCU bus time-out value: 65536 cycles

	this register must be set in the start-up file
	BCU_CON  =  0x4009FFFF;

	Program Memory Unit (PMU):
	ICACHE settings:
	the instruction cache is enabled
	RFB refill operation is terminated on a cache miss which occurs on
	an access to an external burst mode code memory

	this register must be set in the start-up file
	PMU_CON  =  0x04000714;

	external flash settings:
	min. wait cycles between consecutive burst accesses from external
	Flash: 0 wait cycles
	read wait cycles between the initial address and the first data
	cycle: 0 wait cycles
	two address cycles
	one data cycle
	max. number of linear Flash burst data cycles: 32 burst data cycles
	max. number of burst data cycle: 1 data accesses
	#WAIT input operates as a terminate burst function
	#CS0 is activated during burst mode

	this register must be set in the start-up file
	PMU_EIFCON  =  0x00000261;

	External Bus Unit (EBU):

	enable the EBU module

	this register must be set in the start-up file
	EBU_CLC  =  0x00000000;

	External Arbitration:
	EBU is external master
	arbitration inputs are asynchronous
	external bus will not be locked after EBU gained ownership
	enable external accesses to FPI bus
	disable external address extension register reconfiguration
	all accesses from external master are performed in user mode
	disable Time-out
	chip select triggered driver turn-around inactive cycles: 0
	read-write triggered driver turn-around inactive cycles: 0

	this register must be set in the start-up file
	EBU_CON  =  0x00000068;

	Overlay Memory:
	do not activate chip select #CSOVL on an access to memory region 0
	do not activate chip select #CSOVL on an access to memory region 1
	do not activate chip select #CSOVL on an access to memory region 2
	do not activate chip select #CSOVL on an access to memory region 3

	this register must be set in the start-up file
	EBU_EMUCON  =  0x00000000;

	Address Region 0:
	enable memory region 0
	length of the region: 128 Mbyte
	relevant start address (A31 : A0): 0xA0000000
	writes to memory region are disabled
	address generation: demuxed address mode
	external device data width: 32-bit
	address latch enable (ALE) duration: 3 cycles
	byte control signal timing mode: control mode
	cycle 0 is not generated
	variable waitstate insertion is disabled
	pin #WAIT is low active
	read cycle multiplier is 1
	read access waitstates: 48
	cycle multiplier is 16
	write access waitstates: 112
	hold/pause cycle waitstates: 48
	recovery cycles waitstates: 48

	this register must be set in the start-up file
	EBU_ADDSEL0  =  0xA0000001;
	EBU_BUSCON0  =  0xE80261FF;

	Address Region 1:
	enable memory region 1
	length of the region: 128 Mbyte
	relevant start address (A31 : A0): 0xA0000000
	writes to memory region are disabled
	address generation: demuxed address mode
	external device data width: 32-bit
	address latch enable (ALE) duration: 3 cycles
	byte control signal timing mode: control mode
	cycle 0 is not generated
	variable waitstate insertion is disabled
	pin #WAIT is low active
	read cycle multiplier is 1
	read access waitstates: 48
	cycle multiplier is 16
	write access waitstates: 112
	hold/pause cycle waitstates: 48
	recovery cycles waitstates: 48

	this register must be set in the start-up file
	EBU_ADDSEL1  =  0xA0000001;
	EBU_BUSCON1  =  0xE80261FF;

	Address Region 2:
	enable memory region 2
	length of the region: 128 Mbyte
	relevant start address (A31 : A0): 0xA0000000
	writes to memory region are disabled
	address generation: demuxed address mode
	external device data width: 32-bit
	address latch enable (ALE) duration: 3 cycles
	byte control signal timing mode: control mode
	cycle 0 is not generated
	variable waitstate insertion is disabled
	pin #WAIT is low active
	read cycle multiplier is 1
	read access waitstates: 48
	cycle multiplier is 16
	write access waitstates: 112
	hold/pause cycle waitstates: 48
	recovery cycles waitstates: 48

	this register must be set in the start-up file
	EBU_ADDSEL2  =  0xA0000001;
	EBU_BUSCON2  =  0xE80261FF;

	Address Region 3:
	enable memory region 3
	length of the region: 128 Mbyte
	relevant start address (A31 : A0): 0xA0000000
	writes to memory region are disabled
	address generation: demuxed address mode
	external device data width: 32-bit
	address latch enable (ALE) duration: 3 cycles
	byte control signal timing mode: control mode
	cycle 0 is not generated
	variable waitstate insertion is disabled
	pin #WAIT is low active
	read cycle multiplier is 1
	read access waitstates: 48
	cycle multiplier is 16
	write access waitstates: 112
	hold/pause cycle waitstates: 48
	recovery cycles waitstates: 48

	this register must be set in the start-up file
	EBU_ADDSEL3  =  0xA0000001;
	EBU_BUSCON3  =  0xE80261FF;

	Emulator Address Region :
	enable emulator memory region
	length of the region: 16 Mbyte
	relevant start address (A31 : A0): 0xBE000000
	writes to memory region are enabled
	address generation: demuxed address mode
	external device data width: 32-bit
	address latch enable (ALE) duration: 0 cycles
	byte control signal timing mode: chipselect mode
	cycle 0 is generated
	asynchronous waitstate insertion
	pin #WAIT is low active
	read cycle multiplier is 1
	read access waitstates: 1
	cycle multiplier is 1
	write access waitstates: 2
	hold/pause cycle waitstates: 0
	recovery cycles waitstates: 0

	this register must be set in the start-up file
	EBU_EMUAS  =  0xBE000031;
	EBU_EMUBC  =  0x00160280;

	End of Important Settings for the Start-Up File

	Clock System:
	- external clock frequency: 16,000 MHz
	- PLL operation (pin BYPASS = 0)
	- clock factor (N-factor): 10 (pins CLKSEL[2:0] = 0x2)
	- VCO output frequency: 160,000 MHz
	- clock divider (K-factor): 4
	- system clock: 40,000 MHz

	Interrupt System:
	- four arbitration cycles (max. 255 interrupt sources)
	- two clocks per arbitration cycle

	Peripheral Control Processor (PCP):
	- four arbitration cycles (max. 255 PCP channels)
	- two clocks per arbitration cycle
	- use Full Context save area (R[0] - R[7])
	- channel start at context PC
	- the PCP error interrupt is disabled
	- PRAM partitioning is disabled
	- channel watchdog is disabled

	System Start Conditions:

	- the CPU interrupt system is globally disabled

	- the PCP interrupt system is globally disabled

Asynchronous Synchronous Serial Interface 0 (ASC0)

Macros:

	Macro:
		ASC0_ubTxBufFree()
	Description:
		This macro can be used for checking the status of the
		transmit buffer register. The transmit buffer may only be
		written to if it is empty, this implies that the previous
		content of the transmit buffer have been loaded into the
		transmit shift register.
	Returnvalue:
		0 if buffer is not empty, else 1
	Parameters:
		None
Functions:

	Function:
		void ASC0_vInit(void)
	Description:
		This is the initialization function of the ASC0 function
		library. It is assumed that the SFRs used by this library
		are in its reset state.
	Returnvalue:
		None
	Parameters:
		None

	Function:
		void ASC0_vSendData(ushort usData)
	Description:
		This function writes a send data initialization word into
		the transmit buffer register.
		Note:
		In a multiprocessor system the master with this function
		has the possibility to send data to the selected slave. To
		achieve this, the 9th bit must set on zero.
	Returnvalue:
		None
	Parameters:
		usData:
		Data to be send

	Function:
		ushort ASC0_usGetData(void)
	Description:
		This function reads out the content of the receive buffer
		register which contains the received data.
	Returnvalue:
		data that has been received
	Parameters:
		None

Initialization:

	Configuration of the Module Clock:
	- enable the ASC0 module
	- clock divider for normal operation mode: System clock / 1 (= 40,0000
	MHz; 25,000 ns )
	- the ASC0 module is stopped during sleep mode

	Configuration of the ASC0 Baudrate Generator:
	- the ASC0 module clock is 40 MHz
	- additionally reduce serial clock to 2
	- required baud rate = 19,200 kbaud
	- real baud rate     = 19,231 kbaud
	- deviation          = 0,160 %

	Configuration of the ASC0 Operation Mode:
	- 8-bit data asychronous operation with one stop bit

	- receiver is enabled

	Configuration of the used ASC0 Port Pins:

	- P12.13 is used for ASC0 transmit output signal (ASC0_TXD)
	- P12.12 is used for ASC0 receive input signal (ASC0_RXD)

	Configuration of the used ASC0 Interrupts: